Skip to content

A
AIDA-2020 TLU
Commit 7c8005d7 authored by Alvaro Dosil's avatar Alvaro Dosil
Browse files
Options

new FIFO file

parent 86086693
Hide whitespace changes
Inline Side-by-side
Showing with 9 additions and 9 deletions
firmware/ise/ipcore_dir/FIFO.xco
View file @ 7c8005d7
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Tue Feb 12 16:08:05 2013
# Xilinx Core Generator version 14.7
# Date: Fri Aug 29 16:37:03 2014
#
##############################################################
#
......@@ -22,16 +22,16 @@ SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx16
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
......@@ -117,14 +117,14 @@ CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=14
CSET full_threshold_assert_value=13
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=13
CSET full_threshold_negate_value=12
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
......@@ -163,7 +163,7 @@ CSET programmable_empty_type_rdch=Empty
CSET programmable_empty_type_wach=Empty
CSET programmable_empty_type_wdch=Empty
CSET programmable_empty_type_wrch=Empty
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET programmable_full_type_axis=Full
CSET programmable_full_type_rach=Full
CSET programmable_full_type_rdch=Full
......@@ -216,4 +216,4 @@ CSET wuser_width=1
MISC pkg_timestamp=2011-10-22T06:08:52Z
# END Extra information
GENERATE
# CRC: 9755c96c
# CRC: e0f1f870
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment