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AIDA-2020 TLU
Commit 933c60e5 authored by David Cussans's avatar David Cussans
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Bug fixes in SyncGenerator ( part of shutter/spill signal firmware)

parent 350bfc2c
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Showing with 18 additions and 9 deletions
components/tlu/firmware/hdl/SyncGenerator_rtl.vhd
View file @ 933c60e5
...@@ -78,7 +78,7 @@ ARCHITECTURE rtl OF syncGenerator IS ...@@ -78,7 +78,7 @@ ARCHITECTURE rtl OF syncGenerator IS
signal s_trigger_source_select: std_logic_vector(c_SELWIDTH-1 downto 0); signal s_trigger_source_select: std_logic_vector(c_SELWIDTH-1 downto 0);
signal s_counter_lt_t1 , s_counter_lt_t2 , s_counter_lt_t3 , s_counter_gt_cycle : std_logic := '0'; signal s_counter_lt_t1 , s_counter_lt_t2 , s_counter_lt_t3 , s_counter_gt_cycle : std_logic := '0';
signal s_shutter , s_veto : std_logic := '0'; signal s_shutter , s_veto : std_logic := '0';
signal s_threshold_t1,s_threshold_t3,s_threshold_t2, s_internal_cycle_length : unsigned(g_COUNTER_WIDTH-1 downto 0); signal s_threshold_t1,s_threshold_t3,s_threshold_t2, s_internal_cycle_length, s_truncated_counter_value : unsigned(g_COUNTER_WIDTH-1 downto 0);
BEGIN BEGIN
...@@ -97,12 +97,14 @@ BEGIN ...@@ -97,12 +97,14 @@ BEGIN
--! Process to generate a reset signal for counter --! Process to generate a reset signal for counter
--! Will reset ( and hence start to count ) if input trigger is high and --! Will reset ( and hence start to count ) if input trigger is high and
--! the sequence isn't running. --! the sequence isn't running and sequence is enabled.
--! (The sequence isn't running if either the counter exceeds T3 or the top
--! bit of the counter is set and has stopped running.)
p_generateReset: PROCESS (clock_i) p_generateReset: PROCESS (clock_i)
BEGIN BEGIN
IF rising_edge(clock_i) THEN IF rising_edge(clock_i) THEN
if (s_trigger = '1') and if (s_trigger = '1') and
(s_counter_lt_t3 = '0') and ((s_counter_lt_t3 = '0') or (s_counter_value(s_counter_value'left) = '1')) and
(enable_sequence_i = '1') then (enable_sequence_i = '1') then
s_reset_counter<= '1'; s_reset_counter<= '1';
else else
...@@ -131,7 +133,8 @@ BEGIN ...@@ -131,7 +133,8 @@ BEGIN
--! Process to register trigger input --! Process to register trigger input
p_triggerSelect: PROCESS (clock_i) p_triggerSelect: PROCESS (clock_i)
BEGIN BEGIN
IF rising_edge(clock_i) and (strobe_i='1') THEN --IF rising_edge(clock_i) and (strobe_i='1') THEN
IF rising_edge(clock_i) THEN
if (enable_internal_cycle_i='0') then if (enable_internal_cycle_i='0') then
s_trigger <= trigger_sources_i(s_sel); --! Trigger on external signals if not generating internal cycles s_trigger <= trigger_sources_i(s_sel); --! Trigger on external signals if not generating internal cycles
else else
...@@ -148,30 +151,34 @@ BEGIN ...@@ -148,30 +151,34 @@ BEGIN
s_threshold_t3 <= unsigned(threshold_t3_i(s_threshold_t3'range)); s_threshold_t3 <= unsigned(threshold_t3_i(s_threshold_t3'range));
s_internal_cycle_length <= unsigned(internal_cycle_length_i(s_internal_cycle_length'range) ); s_internal_cycle_length <= unsigned(internal_cycle_length_i(s_internal_cycle_length'range) );
-- Truncate the top bit of the counter ( which is only used to halt count
-- when needed.
s_truncated_counter_value <= unsigned( s_counter_value( s_truncated_counter_value'range));
--! Process to drive s_counter_lt_t1 , s_counter_lt_t2, s_counter_lt_t3 --! Process to drive s_counter_lt_t1 , s_counter_lt_t2, s_counter_lt_t3
p_comparators: PROCESS (clock_i) p_comparators: PROCESS (clock_i)
BEGIN BEGIN
IF rising_edge(clock_i) and (strobe_i='1') THEN IF rising_edge(clock_i) and (strobe_i='1') THEN
if unsigned(s_counter_value) < s_threshold_t1 THEN if s_truncated_counter_value < s_threshold_t1 THEN
s_counter_lt_t1 <= '1'; s_counter_lt_t1 <= '1';
else else
s_counter_lt_t1 <= '0'; s_counter_lt_t1 <= '0';
end if; end if;
if unsigned(s_counter_value) < s_threshold_t2 THEN if s_truncated_counter_value < s_threshold_t2 THEN
s_counter_lt_t2 <= '1'; s_counter_lt_t2 <= '1';
else else
s_counter_lt_t2 <= '0'; s_counter_lt_t2 <= '0';
end if; end if;
if unsigned(s_counter_value) < s_threshold_t3 THEN if s_truncated_counter_value < s_threshold_t3 THEN
s_counter_lt_t3 <= '1'; s_counter_lt_t3 <= '1';
else else
s_counter_lt_t3 <= '0'; s_counter_lt_t3 <= '0';
end if; end if;
if unsigned(s_counter_value) > s_internal_cycle_length then if s_truncated_counter_value > s_internal_cycle_length then
s_counter_gt_cycle <= '1'; s_counter_gt_cycle <= '1';
else else
s_counter_gt_cycle <= '0'; s_counter_gt_cycle <= '0';
......
components/tlu/firmware/hdl/stretchPulse4x_rtl.vhd
View file @ 933c60e5
...@@ -11,6 +11,8 @@ USE ieee.std_logic_1164.all; ...@@ -11,6 +11,8 @@ USE ieee.std_logic_1164.all;
--! @author David Cussans --! @author David Cussans
entity stretchPulse4x is entity stretchPulse4x is
generic (
g_FIND_RISING_EDGE : boolean := true); -- ! Set true to look for rising edge of input signal. NB. "false" Not implemented yet.
port ( port (
clk_4x_i : in std_logic; --! system clock clk_4x_i : in std_logic; --! system clock
clk_4x_strobe_i : in std_logic; --! strobes high for one cycle every 4 of clk_4x clk_4x_strobe_i : in std_logic; --! strobes high for one cycle every 4 of clk_4x
......
projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ 933c60e5
...@@ -25,7 +25,7 @@ use work.ipbus.ALL; ...@@ -25,7 +25,7 @@ use work.ipbus.ALL;
entity top is entity top is
generic( generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000011"; -- Firmware revision. Remember to change this as needed. constant FW_VERSION : unsigned(31 downto 0):= X"1e000013"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3 g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4 g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4 g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......
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