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AIDA-2020 TLU
Commit c4e3b974 authored by David Cussans's avatar David Cussans
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* Changed stretchPulse logic to have two words that define width and delay. 

  Added a common delay to all pulses ( needs changing ). Edited triggerlogic to accomodate this.

* Moved s_reset_timestamp_ipbus<='0' , might have been causing a bug in reset

* Edited TPix3_iface to allow the shutter and T0 to be set under IPBus control

* logic_clocks now chooses between external ( from 2-pole Lemo ) and internal ( from sysclk xtal ) clock using a generate statement and generic.

* DUTInterfaces - stretch output trigger pulse to two clock cycles.
parent 133972f3
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Showing with 47 additions and 19 deletions
firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @ c4e3b974
......@@ -114,7 +114,10 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal s_stretch_trig_in : std_logic := '0'; -- ! stretched version of trigger_i
signal s_stretch_trig_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by trigger_i
signal s_trigger_out : std_logic := '0'; -- ! trigger shifted to start on strobe_4x_logic
signal s_trigger_out_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
-- Set length of output trigger here
signal s_trigger_out_sr : std_logic_vector(6 downto 0) := ( others => '1'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
signal s_trigger_out_vector : std_logic_vector(s_trigger_to_dut'range) := ( others => '0' ); -- Nasty bodge - vector copy of s_trigger_out
BEGIN
......@@ -280,7 +283,7 @@ BEGIN
-- Stretch trigger_i pulse to 4 clock cycles on clk4x
if trigger_i = '1' then
s_stretch_trig_in <= '1';
s_stretch_trig_in_sr <= "111";
s_stretch_trig_in_sr <= ( others => '1' );
else
s_stretch_trig_in <= s_stretch_trig_in_sr(0);
s_stretch_trig_in_sr <= '0' & s_stretch_trig_in_sr(s_stretch_trig_in_sr'left downto 1);
......@@ -289,7 +292,7 @@ BEGIN
--
if (strobe_4x_logic_i = '1') and ( s_stretch_trig_in = '1' ) then
s_trigger_out <= '1';
s_trigger_out_sr <= "111";
s_trigger_out_sr <= ( others => '1' );
else
s_trigger_out <= s_trigger_out_sr(0);
s_trigger_out_sr <= '0' & s_trigger_out_sr(s_trigger_out_sr'left downto 1);
......
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ c4e3b974
......@@ -187,9 +187,9 @@ BEGIN
begin -- process ipb_clk_i
if rising_edge(ipbus_clk_i) then
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
s_reset_timestamp_ipbus <= '0';
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
s_reset_timestamp_ipbus <= '0';
case ipbus_i.ipb_addr(2 downto 0) is
when "000" => s_enable_record_ipb <= ipbus_i.ipb_wdata ; -- Enable data record
when "001" => s_reset_timestamp_ipbus <= '1';
......@@ -254,6 +254,7 @@ BEGIN
reset_timestamp_o <= s_reset_timestamp_4x;
-- Change control signals from IPBus clock domain on to clk_4x_logic
-- CHANGE ME - use synchronize registers instead.
p_signals_clk_domain: process (clk_4x_logic_i )
begin -- process p_internal_triggers
if rising_edge(clk_4x_logic_i) then
......
firmware/hdl/common/ipbus_addr_decode.vhd
View file @ c4e3b974
......@@ -36,9 +36,11 @@ package body ipbus_addr_decode is
elsif std_match(addr, "-----------------------0110-----") then
sel := 5; -- i2c_master / base 000000c0 / mask 00000007
elsif std_match(addr, "-----------------------1010-----") then
sel := 6; -- Event_Formatter / base 00000140 / mask 0000001f
sel := 6; -- Event_Formatter / base 00000140 / mask 0000001f
elsif std_match(addr, "-----------------------1011-----") then
sel := 7; -- TPix3_iface / base 00000160 / mask 0000001f
elsif std_match(addr, "-----------------------0000-----") then
sel := 7; -- version / base 00000000 / mask 00000000
sel := 8; -- version / base 00000000 / mask 00000000
else
sel := 99;
end if;
......
firmware/hdl/common/ipbus_ver.vhd
View file @ c4e3b974
......@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a603" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_rdata <= X"a609" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
......
firmware/hdl/common/logic_clocks_rtl.vhd
View file @ c4e3b974
......@@ -69,6 +69,8 @@ library unisim;
use unisim.vcomponents.all;
ENTITY logic_clocks IS
generic (
g_USE_EXTERNAL_CLK : integer := 1); -- --! Set to one to use clock from external clock
PORT(
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
......@@ -208,8 +210,16 @@ BEGIN
I => extclk_p_b, -- Diff_p buffer input (connect directly to top-level port)
IB => extclk_n_b -- Diff_n buffer input (connect directly to top-level port)
);
s_DUT_Clk <= s_extclkG; -- Hard wire for now.
-- Use Generate, since can't figure out how BUFGMUX works
gen_extclk_input: if ( g_USE_EXTERNAL_CLK = 1) generate
s_DUT_Clk <= s_extclkG; -- Hard wire for now.
end generate gen_extclk_input;
gen_intclk_input: if ( g_USE_EXTERNAL_CLK = 0) generate
s_DUT_Clk <= clk_logic_xtal_i;
end generate gen_intclk_input;
extclk_buf : BUFG
port map(
......
firmware/hdl/common/stretchPulse_rtl.vhd
View file @ c4e3b974
......@@ -20,7 +20,7 @@ USE ieee.numeric_std.all;
entity stretchPulse is
generic (
g_PARAM_WIDTH : positive := 4); --! number of bits in parameters (width, delay)
g_PARAM_WIDTH : positive := 5); --! number of bits in parameters (width, delay)
port (
clk_i : in std_logic; --! Active high
......@@ -32,15 +32,21 @@ entity stretchPulse is
end entity stretchPulse;
-- For now just delay the pulse.
architecture rtl of stretchPulse is
signal s_delaySR : std_logic_vector( (2**g_PARAM_WIDTH) -1 downto 0) := ( others => '0' ); -- --! Shift register to generate delay
begin -- architecture rtl
--! Dummy for now. Just pass input to output
--! Delay pulse
p_registerPulse: process (clk_i , pulse_i) is
begin -- process p_registerPulse
if rising_edge(clk_i) then
pulse_o <= pulse_i;
s_delaySR <= s_delaySR( (s_delaySR'left -1) downto 0 ) & pulse_i;
pulse_o <= s_delaySR( to_integer(unsigned(pulseWidth_i)) );
end if;
end process p_registerPulse;
......
firmware/hdl/common/triggerLogic_rtl.vhd
View file @ c4e3b974
......@@ -25,7 +25,8 @@
--! - 0x00000011 RW - trigger pattern - value that gets loaded into CFGLUT5
--! - 0x00000100 RW - bit-0 - internal trigger veto. Set to halt vetos.
--! - 0x00000101 RO - state of external veto
--! - 0x00000111 RW - length / delay for input pulses. 0-31. 0=straight through.Packed as 4 bytes, bits 3-0 = input 0 width, bits 7-4 = input 0 delay, etc.
--! - 0x00000110 RW - stretch of pulses. Additional width = 0-31 clock cycles.
--! - 0x00000111 RW - delay of pulses. 0-31 clock cycles.
--!
--!
......@@ -108,7 +109,8 @@ ARCHITECTURE rtl OF triggerLogic IS
signal s_TriggerPattern : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Pattern to load into LUT for trigger generation
signal s_PulseStretchWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Length of trigger pulses
constant c_PARAM_WIDTH : positive := (g_IPBUS_WIDTH/(2*g_NUM_INPUTS)); -- length of pulse width and delay.
signal s_PulseDelayWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --!number of cycles to delay trigger pulses.
constant c_PARAM_WIDTH : positive := 5; -- length of pulse width and delay.
constant c_N_CTRL : positive := 8;
constant c_N_STAT : positive := 8;
......@@ -171,7 +173,8 @@ BEGIN
s_veto_word <= s_sync_control_from_ipbus(4);
s_internal_veto <= s_veto_word(0);
s_PulseStretchWord <= s_sync_control_from_ipbus(7);
s_PulseStretchWord <= s_sync_control_from_ipbus(6);
s_PulseDelayWord <= s_sync_control_from_ipbus(7);
-- Map the status registers
s_status_to_ipbus(0) <= std_logic_vector(s_post_veto_trigger_counter);
......@@ -182,7 +185,8 @@ BEGIN
s_status_to_ipbus(5) <= s_external_veto_word;
s_external_veto_word(0) <= veto_i;
s_external_veto_word(g_IPBUS_WIDTH-1 downto 1) <= (others=>'0');
s_status_to_ipbus(7) <= s_PulseStretchWord;
-- s_status_to_ipbus(6) <= s_PulseStretchWord;
s_status_to_ipbus(7) <= s_PulseDelayWord;
s_status_to_ipbus(6) <= std_logic_vector(s_aux_trigger_counter);-- Bodge
-- purpose: Delay pulse that loads trigger pattern by one cycle of IPBus clk.
......@@ -205,8 +209,10 @@ BEGIN
clk_i => clk_4x_logic_i,
pulse_i => trigger_i(v_inputNumber),
pulse_o => s_stretchedTriggers(v_inputNumber),
pulsewidth_i => s_PulseStretchWord( (2*v_inputNumber*c_PARAM_WIDTH) + c_PARAM_WIDTH -1 downto 2*v_inputNumber*c_PARAM_WIDTH ),
pulseDelay_i => s_PulseStretchWord( (2*v_inputNumber*c_PARAM_WIDTH) + (2*c_PARAM_WIDTH)-1 downto (2*v_inputNumber*c_PARAM_WIDTH) + c_PARAM_WIDTH )
-- pulsewidth_i => s_PulseStretchWord( (2*v_inputNumber*c_PARAM_WIDTH) + c_PARAM_WIDTH -1 downto 2*v_inputNumber*c_PARAM_WIDTH ),
-- pulseDelay_i => s_PulseDelayWord( (2*v_inputNumber*c_PARAM_WIDTH) + (2*c_PARAM_WIDTH)-1 downto (2*v_inputNumber*c_PARAM_WIDTH) + c_PARAM_WIDTH )
pulsewidth_i => s_PulseStretchWord( c_PARAM_WIDTH-1 downto 0 ),
pulseDelay_i => s_PulseDelayWord( c_PARAM_WIDTH-1 downto 0 )
);
end generate gen_stretchVals;
......
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