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AIDA-2020 TLU
Commit cd6d32d4 authored by David Cussans's avatar David Cussans
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Added more registers to try to improve timing. Still get timing errors

parent 6f451125
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Showing with 19 additions and 7 deletions
firmware/hdl/common/eventFormatter_rtl.vhd
View file @ cd6d32d4
......@@ -175,6 +175,9 @@ ARCHITECTURE rtl OF eventFormatter IS
signal s_enable_spill : std_logic := '1'; -- Enable spill record
signal s_enable_edges : std_logic_vector(g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- Enable edges record
signal s_rst_fifo_d1 , s_rst_fifo_d2 , s_rst_fifo_clk4x : std_logic := '0';
signal s_buffer_full_d1 , s_buffer_full_d2 , s_buffer_full_clk4x : std_logic := '0';
BEGIN
-----------------------------------------------------------------------------
......@@ -261,7 +264,15 @@ BEGIN
s_enable_shutter <= s_enable_record(1);
s_enable_spill <= s_enable_record(2);
s_enable_edges <= s_enable_record(g_NUM_EDGE_INPUTS-1+3 downto 3);
-- move "reset fifo" and "buffer full" signals onto clock4x domain
s_rst_fifo_d1 <= rst_fifo_i;
s_rst_fifo_d2 <= s_rst_fifo_d1;
s_rst_fifo_clk4x <= s_rst_fifo_d2 ;
s_buffer_full_d1 <= buffer_full_i;
s_buffer_full_d2 <= s_buffer_full_d1;
s_buffer_full_clk4x <= s_buffer_full_d2;
end if;
end process p_signals_clk_domain;
......@@ -273,7 +284,7 @@ BEGIN
p_ff_rst: process (clk_4x_logic_i)
begin -- process p_generate_strobes
if rising_edge(clk_4x_logic_i) then
if rst_fifo_i = '1' then
if s_rst_fifo_clk4x = '1' then
s_event_strobe_d1 <= '0';
s_event_strobe_d2 <= '0';
s_event_strobe_d3 <= '0';
......@@ -440,7 +451,7 @@ BEGIN
FIFO_i : entity work.FIFO
PORT MAP (
clk => clk_4x_logic_i,
rst => rst_fifo_i, --logic_reset_i,
rst => s_rst_fifo_clk4x, --logic_reset_i,
din => s_FIFO_i(i),
wr_en => s_FIFO_wr(i),
rd_en => s_FIFO_rd(i),
......@@ -462,10 +473,10 @@ BEGIN
-- Mux to send the read signal to only one FIFO. Priority order: trigger, shutter, edge, spill
-- every trigger word will be read before jump to other data
p_FIFO_rd: process (rst_fifo_i, s_FIFO_empty, buffer_full_i)
p_FIFO_rd: process (s_rst_fifo_clk4x, s_FIFO_empty, s_buffer_full_clk4x)
begin -- process p_generate_strobes
s_FIFO_rd <= (others=>'0');
if buffer_full_i = '0' and rst_fifo_i = '0' then
if s_buffer_full_clk4x = '0' and s_rst_fifo_clk4x = '0' then
l_FIFO_rd: for i in 0 to 3+g_NUM_EDGE_INPUTS-1 loop
if s_FIFO_empty(i) = '0' then
s_FIFO_rd <= std_logic_vector(c_FIFO_rd_mask sll i);
......
firmware/hdl/common/logic_clocks_rtl.vhd
View file @ cd6d32d4
......@@ -113,7 +113,7 @@ ARCHITECTURE rtl OF logic_clocks IS
signal s_logic_reset_ipb, s_logic_reset_ipb_d1 : std_logic := '0';
-- ! Reset signal in IPBus clock domain
signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 : std_logic := '0';
signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 , s_logic_reset_d4 : std_logic := '0';
-- ! reset signal clocked onto logic-clock domain.
signal s_ipbus_ack : std_logic := '0';
......@@ -183,7 +183,8 @@ BEGIN
s_logic_reset_d1 <= s_logic_reset_ipb_d1;
s_logic_reset_d2 <= s_logic_reset_d1;
s_logic_reset_d3 <= s_logic_reset_d2;
s_logic_reset <= s_logic_reset_d2 and ( not s_logic_reset_d3);
s_logic_reset_d4 <= s_logic_reset_d2 and ( not s_logic_reset_d3);
s_logic_reset <= s_logic_reset_d4;
end if;
end process p_reset;
......
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