Copied from fmc_tlu_toplevel_c to fmc_tlu_toplevel_e . Skipped _d since we already had some PCB files with this suffix

Added some new blocks ( fmc_tlu_clock_gen ,fmc_tlu_hdmi_dut_connector , fmc_tlu_threshold_discriminator_dual )

Printed out schematic ( fmc_tlu_v1c.pdf )

Comitting updated schematics for fmc vc . Adding a diagram illustrating coincidence logic. Adding simulation scripts 

test_aida_tlu_trig_counter.py - changed to reflect new address map

Wrote simple firmware to exercise DUT interface pins. Puts out a series of pulses on each pin. See https://elog.phy.bris.ac.uk/elog/AIDA/17 as an example

Wrote a pattern generator function that puts out 0101 pattern then a string of 0. Different number of 01 on different bits

Also, tidying up code and hopefully reducing potential timing-race and meta-stability
issues.

eventFormatter_rtl.vhd