This page describes the reasons for the FMC-nanoFIP update.
--> The current hardware version is v2 here
1. Stand-alone interface
Routing of the complete stand-alone interface, i.e. 16 DATI and the 16 DATO to the mezzanine
2. Vadj
Make the mezzanine adaptable for 3V3 and 2V5 Vad (Vadj to control IO banks)
3. Reliability
Address the following reliability guidelines, as proposed by BI:
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The Reliable Electronics Design - Worksheet & Checklist:
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The updated BLEACC_InputPowerStage.xlsx for the calculation of TJ of the linear regulator which you use to generate the 5VDC starting from the 12VDC, where I have introduced on the carrier board a Zener diode to limit the maximum value for the 12VDC generation.
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The list of rules to apply in order to obtain the “ 3.3V short to 12V or 5V fault exclusion by design”. Such list is agreed with Volker which is well aware about this way of proceeding. “ 3.3V short to 12V or 5V fault exclusion by design”:
a. 3.3V digital lines (16 input, 16 output, JTAG, config, reset etc..) should be located in a different layer in respect to the 12V and 5V layer, separated by a ground plane.
b. The location of the digital lines on the FMC connector should be separated by the 12V input line (part D of the connector ) from a minimum of 2 n/c pins in all direction, so at least they have to be located on the F part, or better in the G or H parts). This action seems not possible for the JTAG lines and the reset, so a ground barrier should be add in between pins. This is a critical point because it is a weakness of the VITA standard pinout.
c. The component placement should keep a separation of 1cm minimum of the components involved in the 5VDC power generation from the digital lines.
d. The line called FPGA_LED_FB should be eliminated or redesigned because it brings the risk of current reinjection from the 5VDC to the 3.3VDC.
e. BGA X-RAY inspection is required.
f. Conformal coating is required.
4. Schematics
- Not to forget request- hope KiCad can do it: When you will describe the pinout, could you please represent it grouped by “functions”? I mean: “those are the pins for the wishbone bus, now these are the pins for the I/O, and here for the JTAG”
5. FMC IO calculations
https://cernbox.cern.ch/index.php/s/410roiAglkTFWr2
(*) At some point we thought TRST was very important to be driven under radiation, finally it seems none of the other groups with equipment under radiation is actually using it. This could save us from the x2 TRST pins.
6. Potential I2C master interface
BI might be interested in having an I2C master for the reconfiguration of the LpGBTx; input from initial discussions is summarized here.