GN4124 local bus clocked by PCIe clock or local oscillator
From Table Table 3-12: GN4124 Clocks’ Pins Settings
Signal Description
|LCLK_MODE_2 | Controls PLL Bypass.|
||‘0’ = LCLK is generated by the PLL, which is configurable. This is
recommended for low and predictable LCLK clock jitter.|R180 OFF, R187
ON|
||‘1’ = LCLK is driven by 125MHz clock generated from the PCI Express
link.|R180 ON, R187 OFF|
|LCLK_MODE_1 |Resets the PLL test clock divider.||
||‘0’ = Resets the PLL test clock divider, so that PLL_TEST_OUT =
‘0’.|R181 OFF, R189 ON|
||‘1’ = PLL_TEST_OUT pin outputs a clock with a frequency of the PLL
clock divided by 1024. This is used for test purposes.|R181 ON, R189
OFF|
|LCLK_MODE_0 |Selects the source for the LCLK PLL.||
||‘0’ = LB_REF_CLK oscillator (20-40MHz). This is recommended for low
and predictable LCLK clock jitter.|R182 OFF, R188 ON|
||‘1’ = 125MHz clock generated from the PCI Express link.|R182 ON, R188
OFF|
Notice that LCLK_MODE_3 is not defined in the datasheet.
The deafault configuration is (pcie.SchDoc):
LCLK_MODE_0 = 0 (25MHz oscillator), LCLK_MODE_1 = 0 (PLL_TEST_OUT off), LCLK_MODE_2 = 0 (PLL on)
Which corresponds to:
R182 OFF, R188 ON, R181 ON, R189 OFF, R180 OFF, R187 ON
LCK_MODE3 is not defined in the GN4124 datasheet but will be set to 1 by default: R183 ON, R190 OFF
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