Review13092010
1. Vadj plane should not be cut under SFP differential lines.
2. L2P Dframe, valid and clkp, should have 10K pull downs. These pulldowns drive the control signals to a known level when the FPGA is not driving them. There have been cases at the time FPGA is removed from reset that garbage data gets clocked into the fifo. This is not on the Gullwing 4124 ref design but it is present on the Altera GN4121 ref design. This is an important one to do.
Pablo 13/10/2010