Schematics Review
Files for review:
Schematics
[pdf]
Altium Designer schematics
[SchDoc]
Clocking diagram
[pdf]
Configuration and JTAG chain diagram
[pdf]
Power supplies diagram
[pdf]
Power supplies consumption
[pdf]
Bill of Materials
[pdf]
Check also the Technical Specifications for more details (still on work)
Schematics review minutes
Date: 02.06.2010 and 03.06.2010
Present: Javier, Erik, Pablo, Tomek, Matthieu
General*
- Use the same decoupling scheme fro all ICs:
- 1nF, 0603, NPO, 50V (0.024 euro)
- 100nF, 0402, X7R, 16V (0.011 euro)
- 1uF, 0603, X7R, 10V (0.025 euro)
- 22uF, 1206, X7R, 6.3V (0.34 euros) - Replace all "0ohm voltage dividers" by 0ohm and 10kohms or 100kohms (to avoid short-cuts on power supplies if both are mounted by mistake).
- Look for resistor network (ladder) for STL terminations.
- Replace X5R capacitors with X7R.
- Reduce BOM to a minimum.
- Remove some of the decoupling capacitors (around FPGA and GN4124).
Power supplies*
- ICs must get all voltages from the same branch (to avoid start-up issues).
- Connect P3V3_FMC to P3V3_PCIe (without regulator).
- Move all voltages generated from P3V3_PCIe to LTM4619 (previously used to generate P3V3_FMC).
- Remove current and voltage measurements, except for P12V_FMC, P3V3_FMC, VADJ and P1V8.
- Move current measurement ICs to the same page as the corresponding regulator (makes schematics clearer).
- Remove ferrites on GN4124 power supplies, except for VTT_AB, VTT_CD and VDDAUX.
- Remove ferrites on digital power supplies of the DDS (DVDD_P1V8 and DVDD_P3V3).
- Add 100nF decoupling capacitors all around the FMC connector.
- Remove multiple names on the same voltage rail.
- Remove P3V_OSC power supply.
- Remove ferrites on OSC1.
- Connect 100kohm resistors (on the output of OSC1) to P3V3_CLEAN_PLLEXT.
- Remove 10kohms resistors in parallel on P1V5 (GN4124 page).
- Merge P1V2_FPGA_CORE and P1V2_MGT.
- Merge P3V3_CLEAN_PLL125 and P3V3_CLEAN_PLLEXT.
- If P5V is not used by the FMC, it can be reduced to 3.5V to reduce power dissipation of linear regulators.
- Add a pull-down resistor on SET pin of OSC5, to be able to enable spread spectrum modulation.
Gennum*
- See mailing list archive for Tim's comments (Thread: PCIe carrier schematics review).
- Check if it is possible to remove the serial 22ohms resistors on P2L data lines.
Clocking*
- Replace TCXO for the GN4124 by a crystal.
- Replace ac-coupling capacitors on GTP clk. ref. with higher values (10nF or so).
- Check TCXO datasheet, to see if ac-coupling + bias is needed.
- Replace 0.1% 100kohms resistors used on OSC1 and OSC2 output with standard 1%.
- Try to find a 3.3V LVDS buffer and remove the 2.5V regulator. Or change the regulator type to use the same as other voltages.
- Configure pin swapping on eSATA connectors.
DDR3*
- Data lines swapping is possible, with some constraints (-> Tom?).
- Remove comment on DDR termination placement.
- Check if R84 is needed.
FPGA*
- Replace R17 by 100kohms.
- Check FPGA symbol (ask DEM how they create such symbols).
FMC*
- Connect TRST_TO_FMC to the IO expander.
- Replace 0603 0ohm resistors for power supplies on HPC rows by 0402.
Voltage translation buffers*
- Look for smaller package.
- Configure pin swapping.
PLLs*
- Check PLL filter component values -> take the same as the WR switch.
SFP*
- Check RD and TD on the SFP symbol.
Misc*
- Check MCP23S17 (IO expander) exposed PAD connection.
- Change all pages to A3.
- Check title boxes.
- Typo in the comment on the left of FMC connector page -> imped_e_nce.
- Remove net names on PGOOD pins (to avoid compilation error and confusion), keep the pull-up for debug.