Project description
Actually this is not a hardware project, but is there to help you find your way in the FMC standard and shows you which FMC Mezzanines and Carriers are being developed in the context of the Open Hardware project. Furthermore it gives practical info that can help you in designing FMC modules.
OHR developments
FMC Carriers
- PCI Express Carrier with 1 FMC slot (LPC). Xilinx Spartan (CERN BE/CO, P.Alvarez)
- Simple PCIe FMC carrier (SPEC). Xilinx Spartan (CERN BE/CO + industry)
- VME FMC Carrier with 2 FMC slots (LPC). Xilinx Spartan (CERN BE/BI, A.Boccardi)
- VME FMC Carrier with 2 FMC slots (HPC). Xilinx Virtex and Sharc DSP (CERN BE/RF, J. Molendijk)
FMC Mezzanines
Digital I/O
-
16-channel TTL I/O
(CERN BE/CO, M.Cattin) - prototype produced (15/2/10)
- programmable as 8 in/8 out, 16 in or 16 out.
Analog to Digital Converters
Overview of specifications of CERN developments at FMCAdcProjects.
-
FmcAdc100M14b4cha: 100 MSPS, 14 bits, 4
channel (CERN
BE/CO) - prototypes
tested
(October 2010)
- Users
- BPM Linac4. To be used on VME carrier (CERN BE/BI, L.Soby, M.Sordet, J.Belleman 1st beam end 2010)
- OASIS general purpose (Deghaye)
- PSB pick-ups, 64 cards needed on PCIe or VME (Belleman - BE/BI, end 2010)
- TERA Hadron therapy, used on specific carrier with USB (N. Malakhov - PH/UGC, received prototype 25/10/2010)
- Agata experiment (M. Bellato - INFN PH/UCM, August 2010, may require 400 cards)
- Culham Centre for Fusion Energy (G. Naylor - CCFE, Aug 2010)
- Users
- FmcAdc100k16b8cha: 100 kSPS, 16 bits, 8 channel (CERN BE/CO) - being designed
- 128 ksps ADC (CERN TE/EPC, Q. King, G. Ramseier) - under design
- 128 kSPS (50 kHz bandwidth) with an ADS1274 Simultaneous Sampling 24-Bit Delta Sigma ADC.
- fixed input range of +/- 11V.
- based on another new design with a DSP, RAM & ADC (ADS1274) combined and a differential serial link.
- The first design is 4-channel, but it may be expanded to 8 channels (ADS1278). - (8/2/10)
- Not clear if this will fit on a single FMC. Most likely a front-end with the ADC in a separate rack will be needed and the FMC will only contain some kind of digital receiver logic. (9/2/10)
- Will use with PCIe carrier.
- User: TE/EPC 64 channels; SVC project (Static Var Compensators, 11x64 signals).
- 125 MSPS, 16 bits, 4 channel ADC (CERN BE/RF,
J.Sanchez)
- 50 Ohm DC-coupled, 70dBFS dynamic range, ENOB ~12, 40MHz analog bandwidth, +/-1V, gain selectable: 0dB/+24dB, thermal offset drift compensation.
- Two low jitter clock inputs and two data clock outputs.
- Design data: EDMS EDA-02068.
- Prototype received (October 2010).
- Needs carrier with HPC connector.
- 2.5 MSPS, 24-bit ADC, 1 channel, +/- 10V input, auto-calibration,
trigger by machine timing (CERN TE/MSC, Giloteaux)
- User: Train-B systems of AD, LEIR, PS, Booster and SPS. End 2010 prototype.
Digital to Analog Converters
- FMC3: 10MSPS, 4 channel, 16 bit, output range +/-10V. - (CERN BE/CO), Project will not start before 2011
- FmcDac4ch16b125MSPS, 4 channel, 16 bit, 125 MSPS DAC (CERN BE/RF,
P.M. Leinonen), schematics ready (April 2010)
- 40 MHz analog BW, AC-coupled, 50 Ohm, 2Vpp or 2Vpp/16 output, 4xSMC, clock generated on MDDS mezzanine output on SMC.
- Needs carrier with HPC connector.
High-performance Time-to-Digital Converter
- FMC6: To be designed (CERN BE/CO) by July 2010 for TE/ABT
- ideas
- A 17ps Time-to-Digital Converter Implemented in 65nm FPGA Technology, C. Favi, E. Charbon
- http://cdsweb.cern.ch/record/989402/files/lhcb-2006-055.pdf
- http://lhcb-doc.web.cern.ch/lhcb-doc/presentations/conferencetalks/postscript/2006presentations/LECC06Jacobsson.pdf (implementation)
- Time intervals measurements and generation methods review, P.Alvarez, 2008
- Users
- E. Carlier (TE/ABT), 1 ns resolution, may use 16-channel TTL I/O for I/O or NIM input?
- A. Boccardi (BE/BI, Synchrotron light monitor), 50 ps resolution, likely another design requiring other front-end.
- ideas
Fine Delay module
-
FMC-Delay-1ns-8cha: 4 channel, 1 ns
resolution (CERN
BE/CO) - Schematics reviewed (November 2010)
- ideas: http://gkasprow.selfip.com/~pkasprow/Creotech/products.pdf (page 5)
- Users
- TE/ABT: Carlier
- CTF3: E.Said (now uses VME board)
Direct Digital Synthesizer
- 0-125 MHz DDS (CERN BE/RF,
J.Sanchez)
- Generates two independent clocks, one 10 MHz reference clock input
- Needs carrier with HPC connector.
FPGA Mezzanine Card (FMC) standard info
FMC standard
- ANSI/VITA 57.1-2008 FPGA Mezzanine Card (FMC) Standard
The FMC standard refers to other standards for the EEPROM data:
- Intelligent Platform Management Interface (Intel)
- Base IPMI commands defined in the PICMG 2.9 specification (CompactPCI System Management)
FMC components
- Front-panels - XTech, Part no. XFM85-0001 (10mm height)
- Spacers
- CERN Stores: 06.61.91.313.1 (10 mm)
- Schroff: 60897-278
- Screws
- CERN Stores (Bossard): 1243896
- FMC connectors - Samtech
Connectors usable with 10mm FMC front-panel
- SMC high-frequency front-panel mount connectors (low enough for 10mm FMC cards)
- Survey of SMA, SMC and MMCX connectors for the use on FMC cards (in French)
- Example order - CERN only
- Multi-pin connector
PCIe front-panel with FMC cutout
The PCI express boards designed as part of the OHR project need a specific front-panel with a cutout for the FMC carrier's front panel.
-
Purcell Brackets
- Example order - CERN only - One-piece design
-
Gompf Brackets
- Example order - CERN only - Three-piece design
FMC Usage notes
Product directories (non OHR developments)
Non-commercial carriers (non OHR developments)
- DESY
- DesyAMC 2 - AMC carrier (page 17)
- CERN
Commercial FMC mezzanines (non OHR developments)
- Dallas Logic - A/D converters
- Curtis Wright - A/D and D/A converters
- Integre Technologies - Camera link and custom designs
- Lyrtech
-
Cryotech
- FMC DSP board with 2 or 4 TI 6-core DSPs used for calculation boosting, equipped with PCIe Gen2 interface. Conceptual stage (15/11/2010)
- FMC 2x 500MHz ADC, 12 bits for EAGLE experiment at Warsaw Laboratory of Heavy Ions - readout of germanium detectors.Conceptual stage (15/11/2010)
- 16 channel ADC, 10 bit, 130Mhz with 4 channel slow DAC. The FMC is up and running, code being written (15/11/2010)
Commercial FMC carriers (non OHR developments)
- Curtis-Wright
- Lyrtech
-
Cryotech
- FMC carrier for 18 or 36 FMC boards in a form of 2U/4U 19" rack. The schematics are almost finished (15/11/2010). We expect to have first prototypes in March. This will be used for 512 channel GEM spectrometer. Design prototype
- Single FMC carrier with Virtex 4 with PowerPC and Gbit Ethernet interface to hold 2x500MHz card. Conceptual stage (15/11/2010)
Other links
- FMC Alliance - refers to these OHR pages
- Adopting VITA 57 (FMC): Reducing FPGA I/O headaches
- A Brief History of FMC (VITA-57), fun background
Erik van der Bij - 15 November 2010