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FMC TDC 1ns 5cha - Gateware
Commit 181fbd42 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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wip cleanup

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hdl/rtl/carrier_info.vhd deleted 100644 → 0
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Misc Info about Carrier
---------------------------------------------------------------------------------------
-- File : carrier_info.vhd
-- Author : auto-generated by wbgen2 from carrier_info.wb
-- Created : 01/22/14 15:17:10
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_info.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrier_info is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_info_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_info_carrier_reserved_i : in std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_info_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
carrier_info_stat_fmc_pres_i : in std_logic;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
carrier_info_stat_p2l_pll_lck_i : in std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
carrier_info_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'DDR3 calibration status' in reg: 'Status'
carrier_info_stat_ddr3_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Status'
carrier_info_stat_reserved_i : in std_logic_vector(27 downto 0);
-- Port for BIT field: 'Green LED' in reg: 'Control'
carrier_info_ctrl_led_green_o : out std_logic;
-- Port for BIT field: 'Red LED' in reg: 'Control'
carrier_info_ctrl_led_red_o : out std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
carrier_info_ctrl_dac_clr_n_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_info_ctrl_reserved_o : out std_logic_vector(28 downto 0);
-- Ports for BIT field: 'State of the reset line' in reg: 'Reset Register'
carrier_info_rst_fmc0_n_o : out std_logic;
carrier_info_rst_fmc0_n_i : in std_logic;
carrier_info_rst_fmc0_n_load_o : out std_logic;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_info_rst_reserved_o : out std_logic_vector(30 downto 0)
);
end carrier_info;
architecture syn of carrier_info is
signal carrier_info_ctrl_led_green_int : std_logic ;
signal carrier_info_ctrl_led_red_int : std_logic ;
signal carrier_info_ctrl_dac_clr_n_int : std_logic ;
signal carrier_info_ctrl_reserved_int : std_logic_vector(28 downto 0);
signal carrier_info_rst_reserved_int : std_logic_vector(30 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_info_ctrl_led_green_int <= '0';
carrier_info_ctrl_led_red_int <= '0';
carrier_info_ctrl_dac_clr_n_int <= '0';
carrier_info_ctrl_reserved_int <= "00000000000000000000000000000";
carrier_info_rst_fmc0_n_load_o <= '0';
carrier_info_rst_reserved_int <= "0000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_info_rst_fmc0_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_info_rst_fmc0_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= carrier_info_carrier_pcb_rev_i;
rddata_reg(15 downto 4) <= carrier_info_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_info_carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= carrier_info_stat_fmc_pres_i;
rddata_reg(1) <= carrier_info_stat_p2l_pll_lck_i;
rddata_reg(2) <= carrier_info_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_info_stat_ddr3_cal_done_i;
rddata_reg(31 downto 4) <= carrier_info_stat_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_info_ctrl_led_green_int <= wrdata_reg(0);
carrier_info_ctrl_led_red_int <= wrdata_reg(1);
carrier_info_ctrl_dac_clr_n_int <= wrdata_reg(2);
carrier_info_ctrl_reserved_int <= wrdata_reg(31 downto 3);
end if;
rddata_reg(0) <= carrier_info_ctrl_led_green_int;
rddata_reg(1) <= carrier_info_ctrl_led_red_int;
rddata_reg(2) <= carrier_info_ctrl_dac_clr_n_int;
rddata_reg(31 downto 3) <= carrier_info_ctrl_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_info_rst_fmc0_n_load_o <= '1';
carrier_info_rst_reserved_int <= wrdata_reg(31 downto 1);
end if;
rddata_reg(0) <= carrier_info_rst_fmc0_n_i;
rddata_reg(31 downto 1) <= carrier_info_rst_reserved_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- PCB revision
-- Reserved register
-- Carrier type
-- FMC presence
-- GN4142 core P2L PLL status
-- System clock PLL status
-- DDR3 calibration status
-- Reserved
-- Green LED
carrier_info_ctrl_led_green_o <= carrier_info_ctrl_led_green_int;
-- Red LED
carrier_info_ctrl_led_red_o <= carrier_info_ctrl_led_red_int;
-- DAC clear
carrier_info_ctrl_dac_clr_n_o <= carrier_info_ctrl_dac_clr_n_int;
-- Reserved
carrier_info_ctrl_reserved_o <= carrier_info_ctrl_reserved_int;
-- State of the reset line
carrier_info_rst_fmc0_n_o <= wrdata_reg(0);
-- Reserved
carrier_info_rst_reserved_o <= carrier_info_rst_reserved_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/rtl/fmc_tdc_core.vhd
View file @ 181fbd42
...@@ -90,33 +90,6 @@ ...@@ -90,33 +90,6 @@
-- Figure 1: TDC core architecture | -- Figure 1: TDC core architecture |
-- | -- |
-- | -- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2014 |
-- Version v6 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v1 GP First version |
-- 06/2012 v2 EG Revamping; Comments added, signals renamed |
-- removed LEDs from top level |
-- new GN4124 core integrated |
-- carrier 1 wire master added |
-- mezzanine I2C master added |
-- mezzanine 1 wire master added |
-- interrupts generator added |
-- changed generation of rst_i |
-- DAC reconfiguration+needed regs added |
-- 06/2012 v3 EG Changes for v2 of TDC mezzanine |
-- Several pinout changes, |
-- acam_ref_clk LVDS instead of CMOS, |
-- no PLL_LD only PLL_STATUS |
-- 04/2013 v4 EG created fmc_tdc_core module; before was all on fmc_tdc_core |
-- 07/2013 v5 EG removed the clks_rsts_manager from the core; will go to top level |
-- 09/2013 v5.1EG added block of comments and architecture drawing |
-- 04/2014 v6 EG added WRabbit support |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -197,13 +170,8 @@ entity fmc_tdc_core is ...@@ -197,13 +170,8 @@ entity fmc_tdc_core is
term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
-- LEDs on TDC mezzanine -- LEDs on TDC mezzanine
tdc_led_status_o : out std_logic; -- amber led on front pannel, division of clk_tdc_i tdc_led_stat_o : out std_logic; -- amber led on front pannel, division of clk_tdc_i
tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 termination tdc_led_trig_o : out std_logic_vector(4 downto 0); -- one amber led on front pannel per Ch
tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 termination
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 termination
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 termination
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 termination
-- White Rabbit control and status registers -- White Rabbit control and status registers
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
...@@ -270,8 +238,7 @@ architecture rtl of fmc_tdc_core is ...@@ -270,8 +238,7 @@ architecture rtl of fmc_tdc_core is
signal utc, wrabbit_ctrl_reg : std_logic_vector(g_width-1 downto 0); signal utc, wrabbit_ctrl_reg : std_logic_vector(g_width-1 downto 0);
-- LEDs -- LEDs
signal acam_channel : std_logic_vector(5 downto 0); signal term_enable_tdc : std_logic_vector(4 downto 0);
signal acam_tstamp_channel : std_logic_vector(2 downto 0);
signal raw_timestamp_valid : std_logic; signal raw_timestamp_valid : std_logic;
signal raw_timestamp : t_acam_timestamp; signal raw_timestamp : t_acam_timestamp;
...@@ -541,6 +508,11 @@ begin ...@@ -541,6 +508,11 @@ begin
); );
---------------------------------------------------------------------------------------------------
-- TSTAMP FINAL FORMAT --
-- ADDITION OF OFFSETS (EX.CALIBRATION) --
-- FILTERING BY PULSE WIDTH --
---------------------------------------------------------------------------------------------------
U_FilterAndConvert : entity work.timestamp_convert_filter U_FilterAndConvert : entity work.timestamp_convert_filter
generic map ( generic map (
g_pulse_width_filter => g_pulse_width_filter, g_pulse_width_filter => g_pulse_width_filter,
...@@ -562,7 +534,6 @@ begin ...@@ -562,7 +534,6 @@ begin
raw_enable_i => raw_enable_i raw_enable_i => raw_enable_i
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- UTC timing source -- -- UTC timing source --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -584,24 +555,10 @@ begin ...@@ -584,24 +555,10 @@ begin
(clk_i => clk_tdc_i, (clk_i => clk_tdc_i,
rst_i => rst_tdc, rst_i => rst_tdc,
utc_p_i => utc_p, utc_p_i => utc_p,
tstamp_wr1_p_i => final_timestamp_valid(0), tstamp_valid_p_i => final_timestamp_valid,
tstamp_wr2_p_i => final_timestamp_valid(1), term_en_i => term_enable_tdc,
tstamp_wr3_p_i => final_timestamp_valid(2), tdc_led_stat_o => tdc_led_stat_o,
tstamp_wr4_p_i => final_timestamp_valid(3), tdc_led_trig_o => tdc_led_trig_o);
tstamp_wr5_p_i => final_timestamp_valid(4),
term_en_5_i => acam_inputs_en(4),
term_en_4_i => acam_inputs_en(3),
term_en_3_i => acam_inputs_en(2),
term_en_2_i => acam_inputs_en(1),
term_en_1_i => acam_inputs_en(0),
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o);
acam_channel <= "000" & acam_tstamp_channel;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- ACAM start_dis, not used -- -- ACAM start_dis, not used --
...@@ -617,6 +574,7 @@ begin ...@@ -617,6 +574,7 @@ begin
d_i => channel_enable_tdc, d_i => channel_enable_tdc,
q_o => channel_enable_sys); q_o => channel_enable_sys);
term_enable_tdc <= acam_inputs_en(4 downto 0);
channel_enable_tdc <= acam_inputs_en(20 downto 16); channel_enable_tdc <= acam_inputs_en(20 downto 16);
channel_enable_o <= channel_enable_sys; channel_enable_o <= channel_enable_sys;
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ 181fbd42
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- File fmc_tdc_mezzanine.vhd | -- File fmc_tdc_mezzanine.vhd |
-- | -- |
-- Description The unit combines | -- Description The unit instantiates |
-- o the TDC core | -- o the TDC core |
-- o the wrabbit_sync unit that is managing the White Rabbit synchronization and | -- o the wrabbit_sync unit that is managing the White Rabbit synchronization and |
-- control signals | -- control signals |
...@@ -21,8 +21,8 @@ ...@@ -21,8 +21,8 @@
-- o the Embedded Interrupt Controller core that concentrates several interrupt | -- o the Embedded Interrupt Controller core that concentrates several interrupt |
-- sources into one WISHBONE interrupt request line. | -- sources into one WISHBONE interrupt request line. |
-- | -- |
-- For the interconnection between the GN4124/VME core and the different cores (TDC, | -- For the interconnection between the host (GN4124/VME core) and the different cores|
-- I2C, 1W, EIC, timestamps memory) the unit instantiates an SDB crossbar. | -- (TDC, I2C, 1W, EIC, timestamps memory) the unit instantiates an SDB crossbar. |
-- | -- |
-- Note that the TDC core uses word addressing, whereas the GN4124/VME cores use byte| -- Note that the TDC core uses word addressing, whereas the GN4124/VME cores use byte|
-- addressing | -- addressing |
...@@ -61,20 +61,6 @@ ...@@ -61,20 +61,6 @@
-- connection with the clks_rsts_manager unit | -- connection with the clks_rsts_manager unit |
-- | -- |
-- | -- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2014 |
-- Version v2 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 07/2013 v1 EG First version |
-- 01/2014 v2 EG Different output for the timestamp data |
-- 01/2014 v3 EG Removed option for timestamps retrieval through DMA |
-- 08/2014 v4 EG Corrected missalignement between wrabbit_tai and wrabbit_tai_p (line 444) |
-- |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -159,12 +145,8 @@ entity fmc_tdc_mezzanine is ...@@ -159,12 +145,8 @@ entity fmc_tdc_mezzanine is
term_en_4_o : out std_logic; term_en_4_o : out std_logic;
term_en_5_o : out std_logic; term_en_5_o : out std_logic;
-- TDC board LEDs -- TDC board LEDs
tdc_led_status_o : out std_logic; tdc_led_stat_o : out std_logic;
tdc_led_trig1_o : out std_logic; tdc_led_trig_o : out std_logic_vector(4 downto 0);
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
-- White Rabbit core -- White Rabbit core
wrabbit_link_up_i : in std_logic; wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic; wrabbit_time_valid_i : in std_logic;
...@@ -346,7 +328,7 @@ begin ...@@ -346,7 +328,7 @@ begin
g_with_dma_readout => g_use_dma_readout, g_with_dma_readout => g_use_dma_readout,
g_with_fifo_readout => g_use_fifo_readout) g_with_fifo_readout => g_use_fifo_readout)
port map port map
( -- clks, rst ( -- clks, rst
clk_tdc_i => clk_tdc_i, clk_tdc_i => clk_tdc_i,
rst_tdc_n_i => rst_tdc_n_i, rst_tdc_n_i => rst_tdc_n_i,
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
...@@ -378,12 +360,8 @@ begin ...@@ -378,12 +360,8 @@ begin
term_en_4_o => term_en_4_o, term_en_4_o => term_en_4_o,
term_en_5_o => term_en_5_o, term_en_5_o => term_en_5_o,
-- TDC board LEDs -- TDC board LEDs
tdc_led_status_o => tdc_led_status_o, tdc_led_stat_o => tdc_led_stat_o,
tdc_led_trig1_o => tdc_led_trig1_o, tdc_led_trig_o => tdc_led_trig_o,
tdc_led_trig2_o => tdc_led_trig2_o,
tdc_led_trig3_o => tdc_led_trig3_o,
tdc_led_trig4_o => tdc_led_trig4_o,
tdc_led_trig5_o => tdc_led_trig5_o,
-- WR stuff -- WR stuff
wrabbit_tai_i => wrabbit_utc_i, wrabbit_tai_i => wrabbit_utc_i,
...@@ -401,48 +379,21 @@ begin ...@@ -401,48 +379,21 @@ begin
timestamp_ready_i => tdc_timestamp_ready, timestamp_ready_i => tdc_timestamp_ready,
raw_enable_i => raw_enable, raw_enable_i => raw_enable,
ts_offset_i => ts_offset, ts_offset_i => ts_offset, -- to be used by the direct readout
reset_seq_i => reset_seq, reset_seq_i => reset_seq,
fmc_id_i => fmc_id_i, fmc_id_i => fmc_id_i,
irq_threshold_o => irq_threshold, irq_threshold_o => irq_threshold,
irq_timeout_o => irq_timeout, irq_timeout_o => irq_timeout,
channel_enable_o => channel_enable channel_enable_o => channel_enable -- from acam config
); );
---------------------------------------------------------------------------------------------------
-- x5 FIFOS --
gen_use_fake_timestamps : if g_use_fake_timestamps_for_sim generate ---------------------------------------------------------------------------------------------------
-- A FIFO with the timestamps of each channel
process(sim_timestamp_i, sim_timestamp_valid_i)
begin
timestamp_valid <= (others => '0');
for i in 0 to 4 loop
if unsigned(sim_timestamp_i.channel) = i then
timestamp(i) <= sim_timestamp_i;
timestamp_valid(i) <= sim_timestamp_valid_i;
end if;
end loop;
end process;
timestamp_ready <= (others => '1');
end generate gen_use_fake_timestamps;
gen_use_real_timestamps : if not g_use_fake_timestamps_for_sim generate
timestamp <= tdc_timestamp;
timestamp_valid <= tdc_timestamp_valid;
tdc_timestamp_ready <= timestamp_ready;
end generate gen_use_real_timestamps;
timestamp_o <= timestamp;
timestamp_valid_o <= timestamp_valid;
gen_fifos : for i in 0 to 4 generate gen_fifos : for i in 0 to 4 generate
U_TheFifo : entity work.timestamp_fifo U_TheFifo : entity work.timestamp_fifo
generic map ( generic map (
g_use_fifo_readout => g_use_fifo_readout) g_use_fifo_readout => g_use_fifo_readout)
...@@ -465,6 +416,9 @@ begin ...@@ -465,6 +416,9 @@ begin
timestamp_stb(i) <= timestamp_valid(i) and timestamp_ready(i); timestamp_stb(i) <= timestamp_valid(i) and timestamp_ready(i);
end generate gen_fifos; end generate gen_fifos;
---------------------------------------------------------------------------------------------------
-- DMA --
---------------------------------------------------------------------------------------------------
gen_with_dma_readout : if g_use_dma_readout generate gen_with_dma_readout : if g_use_dma_readout generate
U_DMA_Engine : entity work.tdc_dma_engine U_DMA_Engine : entity work.tdc_dma_engine
generic map ( generic map (
...@@ -660,6 +614,36 @@ begin ...@@ -660,6 +614,36 @@ begin
temper_o => regs_ow_in.tdc_ow_temp_i, temper_o => regs_ow_in.tdc_ow_temp_i,
id_read_o => regs_ow_in.tdc_ow_csr_valid_i); id_read_o => regs_ow_in.tdc_ow_csr_valid_i);
gen_use_fake_timestamps : if g_use_fake_timestamps_for_sim generate
process(sim_timestamp_i, sim_timestamp_valid_i)
begin
timestamp_valid <= (others => '0');
for i in 0 to 4 loop
if unsigned(sim_timestamp_i.channel) = i then
timestamp(i) <= sim_timestamp_i;
timestamp_valid(i) <= sim_timestamp_valid_i;
end if;
end loop;
end process;
timestamp_ready <= (others => '1');
end generate gen_use_fake_timestamps;
gen_use_real_timestamps : if not g_use_fake_timestamps_for_sim generate
timestamp <= tdc_timestamp;
timestamp_valid <= tdc_timestamp_valid;
tdc_timestamp_ready <= timestamp_ready;
end generate gen_use_real_timestamps;
timestamp_o <= timestamp;
timestamp_valid_o <= timestamp_valid;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture ends -- architecture ends
......
hdl/rtl/fmc_tdc_wrapper.vhd
View file @ 181fbd42
This diff is collapsed.
hdl/rtl/leds_manager.vhd
View file @ 181fbd42
...@@ -21,20 +21,12 @@ ...@@ -21,20 +21,12 @@
-- | O O | 5, STA | -- | O O | 5, STA |
-- |______| | -- |______| |
-- | -- |
-- TDC LEDs: blink upon reception of a pulse. Inverted blinking -- TDC LEDs: blink upon the generation of a valid timestamp |
-- (LED permanently on without pulses on the input) indicates the -- Inverted blinking (LED permanently ON without pulses in the input) indicates the |
-- 50 Ohm termination is active on the channel. -- 50 Ohm termination is active on the channel. |
--
-- TDC LED STA orange:division of the 125 MHz clock; one hz pulses |
-- | -- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) | -- TDC LED STA orange:division of the 125 MHz clock; one hz pulses |
-- Date 05/2012 |
-- Version v0.1 |
-- Depends on |
-- | -- |
---------------- |
-- Last changes |
-- 05/2012 v0.1 EG First version |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -57,11 +49,11 @@ ...@@ -57,11 +49,11 @@
-- Standard library -- Standard library
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific libraries -- Specific libraries
library work; library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.gencores_pkg.all; use work.gencores_pkg.all;
...@@ -76,33 +68,22 @@ entity leds_manager is ...@@ -76,33 +68,22 @@ entity leds_manager is
port port
-- INPUTS -- INPUTS
-- Signals from the clks_rsts_manager -- Signals from the clks_rsts_manager
(clk_i : in std_logic; -- 125 MHz clock (clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- core internal reset, synched with 125 MHz clk rst_i : in std_logic; -- core internal reset, synched with 125 MHz clk
-- Signal from the one_hz_generator unit -- Signal from the one_hz_generator unit
utc_p_i : in std_logic; utc_p_i : in std_logic;
tstamp_wr1_p_i : in std_logic; -- pulse upon the writing of the timestamp
tstamp_wr2_p_i : in std_logic; -- pulse upon the writing of the timestamp
tstamp_wr3_p_i : in std_logic; -- pulse upon the writing of the timestamp
tstamp_wr4_p_i : in std_logic; -- pulse upon the writing of the timestamp
tstamp_wr5_p_i : in std_logic; -- pulse upon the writing of the timestamp
term_en_1_i : in std_logic;
term_en_2_i : in std_logic;
term_en_3_i : in std_logic;
term_en_4_i : in std_logic;
term_en_5_i : in std_logic;
tstamp_valid_p_i : in std_logic_vector(4 downto 0); -- pulse upon writing valid tstamp to FIFO
term_en_i : in std_logic_vector(4 downto 0);
-- OUTPUTS -- OUTPUTS
-- Signals to the LEDs on the TDC front panel -- Signals to the LEDs on the TDC front panel
tdc_led_status_o : out std_logic; -- TDC LED 1: division of 125 MHz tdc_led_stat_o : out std_logic; -- LED STA: division of 125 MHz
tdc_led_trig1_o : out std_logic; -- TDC LED 2: Channel 1 termination enable tdc_led_trig_o : out std_logic_vector(4 downto 0));-- LED 2..5: Blinking indicates generation
tdc_led_trig2_o : out std_logic; -- TDC LED 3: Channel 2 termination enable -- of a valid tstamp;
tdc_led_trig3_o : out std_logic; -- TDC LED 4: Channel 3 termination enable -- permanently ON without pulses
tdc_led_trig4_o : out std_logic; -- TDC LED 5: Channel 4 termination enable -- in the input indicates 50Ohm termination
tdc_led_trig5_o : out std_logic); -- TDC LED 6: Channel 5 termination enable
end leds_manager; end leds_manager;
...@@ -112,18 +93,14 @@ end leds_manager; ...@@ -112,18 +93,14 @@ end leds_manager;
--================================================================================================= --=================================================================================================
architecture rtl of leds_manager is architecture rtl of leds_manager is
signal tdc_led_blink_done : std_logic; signal tdc_led_blink_done : std_logic;
signal visible_blink_length : std_logic_vector(g_width-1 downto 0); signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
signal rst_n, blink_led1, blink_led2 : std_logic; signal rst_n : std_logic;
signal ch1, ch2, ch3, ch4, ch5 : std_logic; signal tdc_led_trig : std_logic_vector (4 downto 0);
signal blink_led3, blink_led4, blink_led5 : std_logic;
signal blink_led : std_logic;
signal acam_channel : std_logic_vector(5 downto 0);
signal tdc_led_trig1, tdc_led_trig2, tdc_led_trig3, tdc_led_trig4, tdc_led_trig5 : std_logic;
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- TDC FRONT PANEL LED 1 -- -- TDC FRONT PANEL LED STA --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -141,11 +118,11 @@ begin ...@@ -141,11 +118,11 @@ begin
begin begin
if rising_edge (clk_i) then if rising_edge (clk_i) then
if rst_i = '1' then if rst_i = '1' then
tdc_led_status_o <= '0'; tdc_led_stat_o <= '0';
elsif utc_p_i = '1' then elsif utc_p_i = '1' then
tdc_led_status_o <= '1'; tdc_led_stat_o <= '1';
elsif tdc_led_blink_done = '1' then elsif tdc_led_blink_done = '1' then
tdc_led_status_o <= '0'; tdc_led_stat_o <= '0';
end if; end if;
end if; end if;
end process; end process;
...@@ -154,7 +131,7 @@ begin ...@@ -154,7 +131,7 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- TDC FRONT PANEL LEDs 2-6 -- -- TDC FRONT PANEL LEDs CH 1-5 --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
rst_n <= not(rst_i); rst_n <= not(rst_i);
...@@ -166,8 +143,8 @@ begin ...@@ -166,8 +143,8 @@ begin
port map port map
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
pulse_i => tstamp_wr1_p_i, pulse_i => tstamp_valid_p_i(0),
extended_o => tdc_led_trig1); extended_o => tdc_led_trig(0));
cmp_extend_ch2_pulse : gc_extend_pulse cmp_extend_ch2_pulse : gc_extend_pulse
generic map generic map
...@@ -175,8 +152,8 @@ begin ...@@ -175,8 +152,8 @@ begin
port map port map
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
pulse_i => tstamp_wr2_p_i, pulse_i => tstamp_valid_p_i(1),
extended_o => tdc_led_trig2); extended_o => tdc_led_trig(1));
cmp_extend_ch3_pulse : gc_extend_pulse cmp_extend_ch3_pulse : gc_extend_pulse
generic map generic map
...@@ -184,8 +161,8 @@ begin ...@@ -184,8 +161,8 @@ begin
port map port map
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
pulse_i => tstamp_wr3_p_i, pulse_i => tstamp_valid_p_i(2),
extended_o => tdc_led_trig3); extended_o => tdc_led_trig(2));
cmp_extend_ch4_pulse : gc_extend_pulse cmp_extend_ch4_pulse : gc_extend_pulse
generic map generic map
...@@ -193,8 +170,8 @@ begin ...@@ -193,8 +170,8 @@ begin
port map port map
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
pulse_i => tstamp_wr4_p_i, pulse_i => tstamp_valid_p_i(3),
extended_o => tdc_led_trig4); extended_o => tdc_led_trig(3));
cmp_extend_ch5_pulse : gc_extend_pulse cmp_extend_ch5_pulse : gc_extend_pulse
generic map generic map
...@@ -202,14 +179,14 @@ begin ...@@ -202,14 +179,14 @@ begin
port map port map
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
pulse_i => tstamp_wr5_p_i, pulse_i => tstamp_valid_p_i(4),
extended_o => tdc_led_trig5); extended_o => tdc_led_trig(4));
tdc_led_trig1_o <= tdc_led_trig1 xor term_en_1_i; tdc_led_trig_o(0) <= tdc_led_trig(0) xor term_en_i(0);
tdc_led_trig2_o <= tdc_led_trig2 xor term_en_2_i; tdc_led_trig_o(1) <= tdc_led_trig(1) xor term_en_i(1);
tdc_led_trig3_o <= tdc_led_trig3 xor term_en_3_i; tdc_led_trig_o(2) <= tdc_led_trig(2) xor term_en_i(2);
tdc_led_trig4_o <= tdc_led_trig4 xor term_en_4_i; tdc_led_trig_o(3) <= tdc_led_trig(3) xor term_en_i(3);
tdc_led_trig5_o <= tdc_led_trig5 xor term_en_5_i; tdc_led_trig_o(4) <= tdc_led_trig(4) xor term_en_i(4);
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/rtl/tdc_core_pkg.vhd
View file @ 181fbd42
...@@ -65,7 +65,7 @@ package tdc_core_pkg is ...@@ -65,7 +65,7 @@ package tdc_core_pkg is
type t_raw_acam_timestamp is record type t_raw_acam_timestamp is record
seconds : std_logic_vector(31 downto 0); -- 32 seconds : std_logic_vector(31 downto 0); -- 32
acam_bins : std_logic_vector(16 downto 0); -- 32 + 17 = 49 acam_bins : std_logic_vector(16 downto 0); -- 32 + 17 = 49
acam_start_nb : std_logic_vector(7 downto 0); acam_start_nb : std_logic_vector(7 downto 0);
roll_over_incr_recent : std_logic; roll_over_incr_recent : std_logic;
clk_i_cycles_offset : std_logic_vector(7 downto 0); -- 60 + 8 = 68 clk_i_cycles_offset : std_logic_vector(7 downto 0); -- 60 + 8 = 68
roll_over_nb : std_logic_vector(15 downto 0); -- 68 + 16 = 84 roll_over_nb : std_logic_vector(15 downto 0); -- 68 + 16 = 84
...@@ -472,12 +472,8 @@ package tdc_core_pkg is ...@@ -472,12 +472,8 @@ package tdc_core_pkg is
term_en_4_o : out std_logic; term_en_4_o : out std_logic;
term_en_5_o : out std_logic; term_en_5_o : out std_logic;
-- TDC board LEDs -- TDC board LEDs
tdc_led_status_o : out std_logic; tdc_led_stat_o : out std_logic;
tdc_led_trig1_o : out std_logic; tdc_led_trig_o : out std_logic_vector(4 downto 0);
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
-- White Rabbit core -- White Rabbit core
wrabbit_link_up_i : in std_logic; wrabbit_link_up_i : in std_logic;
wrabbit_time_valid_i : in std_logic; wrabbit_time_valid_i : in std_logic;
...@@ -541,12 +537,8 @@ package tdc_core_pkg is ...@@ -541,12 +537,8 @@ package tdc_core_pkg is
term_en_3_o : out std_logic; term_en_3_o : out std_logic;
term_en_4_o : out std_logic; term_en_4_o : out std_logic;
term_en_5_o : out std_logic; term_en_5_o : out std_logic;
tdc_led_status_o : out std_logic; tdc_led_stat_o : out std_logic;
tdc_led_trig1_o : out std_logic; tdc_led_trig_o : out std_logic_vector(4 downto 0);
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0); wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0); wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0);
wrabbit_synched_i : in std_logic; wrabbit_synched_i : in std_logic;
...@@ -816,40 +808,6 @@ package tdc_core_pkg is ...@@ -816,40 +808,6 @@ package tdc_core_pkg is
end component; end component;
---------------------------------------------------------------------------------------------------
component carrier_info
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
carrier_info_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
carrier_info_carrier_reserved_i : in std_logic_vector(11 downto 0);
carrier_info_carrier_type_i : in std_logic_vector(15 downto 0);
carrier_info_stat_fmc_pres_i : in std_logic;
carrier_info_stat_p2l_pll_lck_i : in std_logic;
carrier_info_stat_sys_pll_lck_i : in std_logic;
carrier_info_stat_ddr3_cal_done_i : in std_logic;
carrier_info_stat_reserved_i : in std_logic_vector(27 downto 0);
carrier_info_ctrl_led_green_o : out std_logic;
carrier_info_ctrl_led_red_o : out std_logic;
carrier_info_ctrl_dac_clr_n_o : out std_logic;
carrier_info_ctrl_reserved_o : out std_logic_vector(28 downto 0);
carrier_info_rst_fmc0_n_o : out std_logic;
carrier_info_rst_fmc0_n_i : in std_logic;
carrier_info_rst_fmc0_n_load_o : out std_logic;
carrier_info_rst_reserved_o : out std_logic_vector(30 downto 0));
end component carrier_info;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component acam_databus_interface component acam_databus_interface
port port
......
hdl/rtl/timestamp_fifo.vhd
View file @ 181fbd42
...@@ -129,13 +129,19 @@ begin ...@@ -129,13 +129,19 @@ begin
raw_enable_o <= channel_reg_out.csr_raw_mode_o; raw_enable_o <= channel_reg_out.csr_raw_mode_o;
---------------------------------------------------------------------------------------------------
-- Tstamps subtraction to calculate rising timestap deltas --
---------------------------------------------------------------------------------------------------
-- Latching of the last rising edge tstamp
p_latch_ref_timestamp : process(clk_sys_i) p_latch_ref_timestamp : process(clk_sys_i)
begin begin
if rising_edge(clk_sys_i) then if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' or enable_i = '0' then if rst_sys_n_i = '0' or enable_i = '0' then
ref_valid <= '0'; ref_valid <= '0';
else else
-- latch only the last rising edge TS -- latch only the last rising edge tstamp
if (enable_i = '1' and timestamp_valid_i = '1') then if (enable_i = '1' and timestamp_valid_i = '1') then
ref_valid <= '1'; ref_valid <= '1';
ref_ts <= timestamp_i; ref_ts <= timestamp_i;
...@@ -146,6 +152,7 @@ begin ...@@ -146,6 +152,7 @@ begin
sub_valid <= ref_valid and timestamp_valid_i; sub_valid <= ref_valid and timestamp_valid_i;
-- Tstamp pipelined subtractor
U_Subtractor : entity work.tdc_ts_sub U_Subtractor : entity work.tdc_ts_sub
port map ( port map (
clk_i => clk_sys_i, clk_i => clk_sys_i,
...@@ -157,6 +164,7 @@ begin ...@@ -157,6 +164,7 @@ begin
valid_o => sub_out_valid, valid_o => sub_out_valid,
q_o => sub_result); q_o => sub_result);
-- Deltas calculations
p_latch_deltas : process(clk_sys_i) p_latch_deltas : process(clk_sys_i)
begin begin
if rising_edge(clk_sys_i) then if rising_edge(clk_sys_i) then
......
hdl/top/spec/wr_spec_tdc.vhd
View file @ 181fbd42
...@@ -355,7 +355,7 @@ architecture rtl of wr_spec_tdc is ...@@ -355,7 +355,7 @@ architecture rtl of wr_spec_tdc is
constant c_WB_LAYOUT_MASK : constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := ( t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes : not(0x40 -1) = not(0x3F) = c0 c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes : not(0x40 -1) = not(0x3F) = c0
c_WB_SLAVE_FMC_TDC => x"0002_0000"); -- 0x20000 bytes : not(0x6200 -1) = not(0x1FFF) = e0000 c_WB_SLAVE_FMC_TDC => x"0002_0000");
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- Signals -- Signals
...@@ -664,7 +664,7 @@ begin ...@@ -664,7 +664,7 @@ begin
cmp_fmc_tdc_mezzanine : entity work.fmc_tdc_wrapper cmp_fmc_tdc_mezzanine : entity work.fmc_tdc_wrapper
generic map ( generic map (
g_simulation => g_simulation, g_simulation => g_simulation,
g_with_direct_readout => false, g_with_direct_readout => false, -- for embedded applications, like WRTD
g_use_dma_readout => g_use_dma_readout, g_use_dma_readout => g_use_dma_readout,
g_use_fifo_readout => true, g_use_fifo_readout => true,
g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim) g_use_fake_timestamps_for_sim => g_use_fake_timestamps_for_sim)
...@@ -702,12 +702,12 @@ begin ...@@ -702,12 +702,12 @@ begin
term_en_3_o => fmc0_tdc_term_en_3_o, term_en_3_o => fmc0_tdc_term_en_3_o,
term_en_4_o => fmc0_tdc_term_en_4_o, term_en_4_o => fmc0_tdc_term_en_4_o,
term_en_5_o => fmc0_tdc_term_en_5_o, term_en_5_o => fmc0_tdc_term_en_5_o,
tdc_led_status_o => fmc0_tdc_led_status_o, tdc_led_stat_o => fmc0_tdc_led_status_o,
tdc_led_trig1_o => fmc0_tdc_led_trig1_o, tdc_led_trig_o(0) => fmc0_tdc_led_trig1_o,
tdc_led_trig2_o => fmc0_tdc_led_trig2_o, tdc_led_trig_o(1) => fmc0_tdc_led_trig2_o,
tdc_led_trig3_o => fmc0_tdc_led_trig3_o, tdc_led_trig_o(2) => fmc0_tdc_led_trig3_o,
tdc_led_trig4_o => fmc0_tdc_led_trig4_o, tdc_led_trig_o(3) => fmc0_tdc_led_trig4_o,
tdc_led_trig5_o => fmc0_tdc_led_trig5_o, tdc_led_trig_o(4) => fmc0_tdc_led_trig5_o,
mezz_scl_o => tdc_scl_oen, mezz_scl_o => tdc_scl_oen,
mezz_sda_o => tdc_sda_oen, mezz_sda_o => tdc_sda_oen,
......
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