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FMC TDC 1ns 5cha - Gateware
Commit 3fcb563b authored by egousiou's avatar egousiou
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updated spec tdc simulation testbench 

git-svn-id: http://svn.ohwr.org/fmc-tdc@135 85dfdc96-de2c-444c-878d-45b388be74a9
parent 5e2f8235
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Showing with 1023 additions and 20 deletions
hdl/sim/spec/data_vectors/acam_test_cmd0.vec 0 → 100644
View file @ 3fcb563b
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
-- Gonzalo: 3 writings outside of the BAR defined memory space to check that
-- the BFM model does not forward them to the Local bus
wr 0000000040000808 F 0001F04C
wait %d50
wr 0000000040000800 F 00021040
wait %d50
wr 0000000040000800 F 00025000
wait %d50
-- Gonzalo: 5 reads inside Matthieu's core memory space to check that the core
-- does not forward them to the wishbone bus
rd 0000000000000000 F 0000A0A1
wait %d20
rd 0000000000000004 F 0000A0A2
wait %d20
rd 0000000000000008 F 0000A0A3
wait %d20
rd 000000000000000C F 0000A0A4
wait %d20
rd 0000000000000010 F 0000A0A5
wait %d60
-- Gonzalo: actual wr and rd for test
wr 0000000000005000 F 0000FC81
wait %d50
wr 000000000000502C F 00FF0000
wait %d50
rd 0000000000080000 F 0000FC81
wait %d50
rd 000000000008002C F 00FF0000
wait %d50
wr 0000000000080030 F 04000000
wait %d50
rd 0000000000080030 F 04000000
wait %d50
hdl/sim/spec/data_vectors/atdc_test_cmd0.vec 0 → 100644
View file @ 3fcb563b
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
---- Gonzalo: 3 writings outside of the BAR defined memory space to check that
---- the BFM model does not forward them to the Local bus
--wr 0000000040000808 F 0001F04C
--wait %d20
--wr 0000000040000800 F 00021040
--wait %d20
--wr 0000000040000800 F 00025000
--wait %d60
---- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
---- does not forward them to the wishbone bus
--rd 0000000000000000 F 0000A0A1
--wait %d20
--rd 0000000000000004 F 0000A0A2
--wait %d20
--rd 0000000000000008 F 0000A0A3
--wait %d60
-- Gonzalo: actual wr and rd on the application memory space for test
-- writing stuff on the TDC config
--wr 0000000000005000 F 00000040
--wait %d20
--wr 0000000000005004 F 00000000
--wait %d20
--wr 0000000000005008 F 00000000
--wait %d60
-- writing stuff for the ACAM config
wr 0000000000005000 F 01F0FC81
wait %d20
wr 0000000000005004 F 00000000
wait %d20
wr 0000000000005008 F 00000E02
wait %d60
-- loading the utc time
wr 00000000000050FC F 00000200
wait %d200
-- loading the acam config
wr 00000000000050FC F 00000004
wait %d200
-- reading back the acam config
wr 00000000000050FC F 00000008
wait %d200
-- activate acquisition
wr 00000000000050FC F 00000001
wait %d540000
-- read circular buffer wr pointer
rd 000000000000509C F 00000000
wait %d200
-- prepare and launch DMA transfer
wr 000000000000000C F 36EF8000
wait %d20
wr 0000000000000014 F 00000210
wait %d100
wr 0000000000000000 F 00000001
wait %d100
-- deactivate acquisition
wr 00000000000800FC F 00000002
wait %d200
-- read acam status
wr 00000000000800FC F 00000010
wait %d100
rd 0000000000080070 F 00000000
wait %d100
-- read acam ififo1
wr 00000000000800FC F 00000020
wait %d100
rd 0000000000080060 F 00000000
wait %d100
-- read acam ififo2
wr 00000000000800FC F 00000040
wait %d100
rd 0000000000080064 F 00000000
wait %d100
-- read acam start01 register
wr 00000000000800FC F 00000080
wait %d100
rd 0000000000080068 F 00000000
wait %d100
-- reset acam
wr 00000000000800FC F 00000100
wait %d200
--rd 0000000000080000 F 00001234
--wait %d20
--rd 0000000000080004 F 00005678
--wait %d20
--rd 0000000000080008 F 0000abcd
--wait %d20
--rd 000000000008000C F 0000ef90
--wait %d60
--
--wr 00000000000800FC F 00000001
--wait %d100
--wr 00000000000800FC F 00000002
--wait %d100
---- Gonzalo: registers inside Matthieu's core memory space are written with the
---- settings for DMA transfer
--
---- Start address on the carrier local memory
--wr 0000000000000008 F 00000000
--wait %d20
--
---- Start addresses on the PCI host memory
--wr 000000000000000C F 0000A0A4
--wait %d20
--wr 0000000000000010 F 0000A0A5
--wait %d20
--
---- Transfer length
--wr 0000000000000014 F 00000060
--wait %d20
--
---- Chain control
--wr 0000000000000020 F 00000000
--wait %d60
--
---- Start transfer through the Control register and check through the status register
--wr 0000000000000000 F 00000001
--wait %d100
--rd 0000000000000004 F 00000001
--wait %d100
--
--
hdl/sim/spec/data_vectors/memo_test_cmd0.vec 0 → 100644
View file @ 3fcb563b
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
-- Gonzalo: 3 writings outside of the BAR defined memory space to check that
-- the BFM model does not forward them to the Local bus
wr 0000000040000808 F 0001F04C
wait %d20
wr 0000000040000800 F 00021040
wait %d20
wr 0000000040000800 F 00025000
wait %d60
-- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
-- does not forward them to the wishbone bus
rd 0000000000000000 F 0000A0A1
wait %d20
rd 0000000000000004 F 0000A0A2
wait %d20
rd 0000000000000008 F 0000A0A3
wait %d60
-- Gonzalo: actual wr and rd on the application memory space for test
wr 0000000000080000 F 00001234
wait %d20
wr 0000000000080004 F 00005678
wait %d20
wr 0000000000080008 F 0000abcd
wait %d20
wr 000000000008000C F 0000ef90
wait %d60
rd 0000000000080000 F 00001234
wait %d20
rd 0000000000080004 F 00005678
wait %d20
rd 0000000000080008 F 0000abcd
wait %d20
rd 000000000008000C F 0000ef90
wait %d60
wr 0000000000080100 F 00000001
wait %d100
wr 0000000000080100 F 00000002
wait %d100
-- Gonzalo: registers inside Matthieu's core memory space are written with the
-- settings for DMA transfer
-- Start address on the carrier local memory
wr 0000000000000008 F 00000000
wait %d20
-- Start addresses on the PCI host memory
wr 000000000000000C F 0000A0A4
wait %d20
wr 0000000000000010 F 0000A0A5
wait %d20
-- Transfer length
wr 0000000000000014 F 00000060
wait %d20
-- Chain control
wr 0000000000000020 F 00000000
wait %d60
-- Start transfer through the Control register and check through the status register
wr 0000000000000000 F 00000001
wait %d100
rd 0000000000000004 F 00000001
wait %d100
hdl/sim/spec/data_vectors/pulses.txt 0 → 100644
View file @ 3fcb563b
2600 us 1 5 us
800 us 2 505 ns
162 ps 3 505 ns
500 us 4 505 ns
400 ps 1 505 ns
18 ps 5 505 ns
600 ns 1 100 ps
110 ps 2 100 ps
110 ps 3 100 ps
\ No newline at end of file
hdl/sim/spec/spec_fmc_tdc_sim.xise 0 → 100644
View file @ 3fcb563b
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<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="tb_tdc_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="tb_tdc_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="tb_tdc_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="tb_tdc_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="tb_tdc" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_tdc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_tdc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_tdc" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|tb_tdc|behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="newfmctdc" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-02-23T10:13:31" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="243C892F40BA46AEB0B289A48EEA2D35" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/testbench/spec/tb_tdc.vhd
View file @ 3fcb563b
......@@ -30,7 +30,7 @@ architecture behavioral of tb_tdc is
generic(
g_span : integer :=32;
g_width : integer :=32;
values_for_simulation : boolean :=FALSE
values_for_simul : boolean :=FALSE
);
port(
-- interface with GNUM circuit
......@@ -58,12 +58,12 @@ architecture behavioral of tb_tdc is
p_rd_d_rdy_i: in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
spare_o : out std_logic;
-- interface signals with PLL circuit
acam_refclk_i : in std_logic;
pll_ld_i : in std_logic;
pll_refmon_i : in std_logic;
acam_refclk_p_i : in std_logic;
acam_refclk_n_i : in std_logic;
--pll_ld_i : in std_logic;
--pll_refmon_i : in std_logic;
pll_sdo_i : in std_logic;
pll_status_i : in std_logic;
......@@ -86,8 +86,8 @@ architecture behavioral of tb_tdc is
data_bus_io : inout std_logic_vector(27 downto 0);
ef1_i : in std_logic;
ef2_i : in std_logic;
lf1_i : in std_logic;
lf2_i : in std_logic;
--lf1_i : in std_logic;
--lf2_i : in std_logic;
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic;
......@@ -96,16 +96,28 @@ architecture behavioral of tb_tdc is
wr_n_o : out std_logic;
-- other signals on the tdc card
tdc_in_fpga_1_i : in std_logic;
tdc_in_fpga_2_i : in std_logic;
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
mute_inputs_o : out std_logic;
enable_inputs_o : out std_logic;
tdc_led_status_o : out std_logic;
tdc_led_trig1_o : out std_logic;
tdc_led_trig2_o : out std_logic;
tdc_led_trig3_o : out std_logic;
tdc_led_trig4_o : out std_logic;
tdc_led_trig5_o : out std_logic;
carrier_one_wire_b : inout std_logic;
sys_scl_b : inout std_logic;
sys_sda_b : inout std_logic;
mezz_one_wire_b : inout std_logic;
pcb_ver_i : in std_logic_vector(3 downto 0);
prsnt_m2c_n_i : in std_logic;
-- other signals on the spec card
spec_aux0_i : in std_logic;
spec_aux1_i : in std_logic;
......@@ -283,7 +295,8 @@ constant start_retrig_period : time:= 512 ns;
-- Maximum width of a command string
constant STRING_MAX : integer := 256;
signal acam_refclk_i : std_logic:='0';
signal acam_refclk_i : std_logic:='0';
signal acam_refclk_n_i : std_logic:='1';
signal tdc_clk_p_i : std_logic:='0';
signal tdc_clk_n_i : std_logic:='1';
signal spec_clk_i : std_logic:='0';
......@@ -389,7 +402,7 @@ begin
generic map(
g_span => 32,
g_width => 32,
values_for_simulation => TRUE
values_for_simul => TRUE
)
port map(
-- interface with GNUM circuit
......@@ -415,12 +428,12 @@ begin
p_rd_d_rdy_i => p_rd_d_rdy,
tx_error_i => tx_error,
irq_p_o => irq_p,
spare_o => spare,
-- interface with PLL circuit
acam_refclk_i => acam_refclk_i,
pll_ld_i => pll_ld_i,
pll_refmon_i => pll_refmon_i,
acam_refclk_p_i => acam_refclk_i,
acam_refclk_n_i => acam_refclk_n_i,
--pll_ld_i => pll_ld_i,
--pll_refmon_i => pll_refmon_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
......@@ -443,8 +456,8 @@ begin
data_bus_io => data_bus_io,
ef1_i => ef1_i,
ef2_i => ef2_i,
lf1_i => lf1_i,
lf2_i => lf2_i,
--lf1_i => lf1_i,
--lf2_i => lf2_i,
address_o => address_o,
cs_n_o => cs_n_o,
......@@ -454,16 +467,27 @@ begin
-- other signals on the tdc card
tdc_in_fpga_5_i => tdc_in_fpga_5,
mute_inputs_o => mute_inputs,
tdc_in_fpga_1_i => '0',
tdc_in_fpga_2_i => '0',
tdc_in_fpga_3_i => '0',
tdc_in_fpga_4_i => '0',
enable_inputs_o => mute_inputs,
tdc_led_status_o => tdc_led_status,
tdc_led_trig1_o => tdc_led_trig1,
tdc_led_trig2_o => tdc_led_trig2,
tdc_led_trig3_o => tdc_led_trig3,
tdc_led_trig4_o => tdc_led_trig4,
tdc_led_trig5_o => tdc_led_trig5,
-- other signals on the spec card
carrier_one_wire_b => open,
sys_scl_b => open,
sys_sda_b => open,
mezz_one_wire_b => open,
pcb_ver_i => (others => '0'),
prsnt_m2c_n_i => '0',
spec_aux0_i => spec_aux0_i,
spec_aux1_i => spec_aux1_i,
spec_aux2_o => spec_aux2_o,
......@@ -627,6 +651,9 @@ begin
if pll_cs_o ='1' and rst_n ='1' then
tdc_clk_p_i <= not (tdc_clk_p_i) after 1 ns;
tdc_clk_n_i <= not (tdc_clk_n_i) after 1 ns;
pll_status_i <= '1';
end if;
wait for pll_clk_period/2;
end process;
......@@ -638,6 +665,8 @@ begin
end if;
wait for pll_clk_period*2;
end process;
acam_refclk_n_i <= not acam_refclk_i;
spec_clock: process
begin
......
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