updated spec tdc simulation testbench

git-svn-id: http://svn.ohwr.org/fmc-tdc@135 85dfdc96-de2c-444c-878d-45b388be74a9

updated spec tdc simulation testbench
git-svn-id: http://svn.ohwr.org/fmc-tdc@135 85dfdc96-de2c-444c-878d-45b388be74a9
3fcb563b · egousiou · 5e2f8235 · 3fcb563b · 3fcb563b · 3fcb563b
Commit 3fcb563b authored Oct 14, 2013 by egousiou
6 changed files
--- a/hdl/sim/spec/data_vectors/acam_test_cmd0.vec
+++ b/hdl/sim/spec/data_vectors/acam_test_cmd0.vec
+-------------------------------------------------------------------------------
+-- acam_test.vec
+-------------------------------------------------------------------------------
+-- Select the GN4124 Primary BFM
+model 0
+
+-- Initialize the BFM to its default state
+init
+
+-------------------------------------------------------------------------------
+-- Initialize the Primary GN412x BFM model
+-------------------------------------------------------------------------------
+-- These address ranges will generate traffic from the BFM to the FPGA
+-- bar BAR ADDR SIZE VC TC S
+bar     0 0000000000000000 00100000 0 7 0
+
+-- This allocates a RAM block inside the BFM for the FPGA to access
+-- bfm_bar BAR ADDR SIZE
+bfm_bar 0 0000000040000000 20000000
+bfm_bar 1 0000000020000000 20000000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d50000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d60000
+
+-------------------------------------------------------------------------------
+-- Access the tdc core register space
+-------------------------------------------------------------------------------
+-- the following writes will go out in a single packet
+
+-- Gonzalo: 3 writings outside of the BAR defined memory space to check that 
+-- the BFM model does not forward them to the Local bus
+
+wr 0000000040000808 F 0001F04C
+wait   %d50
+wr 0000000040000800 F 00021040
+wait   %d50
+wr 0000000040000800 F 00025000
+wait   %d50
+
+-- Gonzalo: 5 reads inside Matthieu's core memory space to check that the core
+-- does not forward them to the wishbone bus
+
+rd 0000000000000000 F 0000A0A1
+wait   %d20
+rd 0000000000000004 F 0000A0A2
+wait   %d20
+rd 0000000000000008 F 0000A0A3
+wait   %d20
+rd 000000000000000C F 0000A0A4
+wait   %d20
+rd 0000000000000010 F 0000A0A5
+wait   %d60
+
+-- Gonzalo: actual wr and rd for test
+
+wr 0000000000005000 F 0000FC81
+wait   %d50
+wr 000000000000502C F 00FF0000
+wait   %d50
+rd 0000000000080000 F 0000FC81
+wait   %d50
+rd 000000000008002C F 00FF0000
+wait   %d50
+
+wr 0000000000080030 F 04000000
+wait   %d50
+rd 0000000000080030 F 04000000
+wait   %d50
--- a/hdl/sim/spec/data_vectors/atdc_test_cmd0.vec
+++ b/hdl/sim/spec/data_vectors/atdc_test_cmd0.vec
+-------------------------------------------------------------------------------
+-- acam_test.vec
+-------------------------------------------------------------------------------
+-- Select the GN4124 Primary BFM
+model 0
+
+-- Initialize the BFM to its default state
+init
+
+-------------------------------------------------------------------------------
+-- Initialize the Primary GN412x BFM model
+-------------------------------------------------------------------------------
+-- These address ranges will generate traffic from the BFM to the FPGA
+-- bar BAR ADDR SIZE VC TC S
+bar     0 0000000000000000 00100000 0 7 0
+
+-- This allocates a RAM block inside the BFM for the FPGA to access
+-- bfm_bar BAR ADDR SIZE
+bfm_bar 0 0000000040000000 20000000
+bfm_bar 1 0000000020000000 20000000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d50000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d60000
+
+-------------------------------------------------------------------------------
+-- Access the tdc core register space
+-------------------------------------------------------------------------------
+-- the following writes will go out in a single packet
+
+---- Gonzalo: 3 writings outside of the BAR defined memory space to check that 
+---- the BFM model does not forward them to the Local bus
+--wr 0000000040000808 F 0001F04C
+--wait   %d20
+--wr 0000000040000800 F 00021040
+--wait   %d20
+--wr 0000000040000800 F 00025000
+--wait   %d60
+
+---- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
+---- does not forward them to the wishbone bus
+--rd 0000000000000000 F 0000A0A1
+--wait   %d20
+--rd 0000000000000004 F 0000A0A2
+--wait   %d20
+--rd 0000000000000008 F 0000A0A3
+--wait   %d60
+
+-- Gonzalo: actual wr and rd on the application memory space for test
+-- writing stuff on the TDC config
+--wr 0000000000005000 F 00000040
+--wait   %d20
+--wr 0000000000005004 F 00000000
+--wait   %d20
+--wr 0000000000005008 F 00000000
+--wait   %d60
+
+-- writing stuff for the ACAM config
+wr 0000000000005000 F 01F0FC81
+wait   %d20
+wr 0000000000005004 F 00000000
+wait   %d20
+wr 0000000000005008 F 00000E02
+wait   %d60
+
+-- loading the utc time
+wr 00000000000050FC F 00000200
+wait   %d200
+
+-- loading the acam config
+wr 00000000000050FC F 00000004
+wait   %d200
+
+-- reading back the acam config
+wr 00000000000050FC F 00000008
+wait   %d200
+
+-- activate acquisition
+wr 00000000000050FC F 00000001
+wait   %d540000
+
+-- read circular buffer wr pointer
+rd 000000000000509C F 00000000
+wait   %d200
+
+-- prepare and launch DMA transfer
+wr 000000000000000C F 36EF8000
+wait   %d20
+wr 0000000000000014 F 00000210
+wait   %d100
+
+wr 0000000000000000 F 00000001
+wait   %d100
+
+
+-- deactivate acquisition
+wr 00000000000800FC F 00000002
+wait   %d200
+
+-- read acam status
+wr 00000000000800FC F 00000010
+wait   %d100
+rd 0000000000080070 F 00000000
+wait   %d100
+
+-- read acam ififo1
+wr 00000000000800FC F 00000020
+wait   %d100
+rd 0000000000080060 F 00000000
+wait   %d100
+
+-- read acam ififo2
+wr 00000000000800FC F 00000040
+wait   %d100
+rd 0000000000080064 F 00000000
+wait   %d100
+
+-- read acam start01 register
+wr 00000000000800FC F 00000080
+wait   %d100
+rd 0000000000080068 F 00000000
+wait   %d100
+
+-- reset acam
+wr 00000000000800FC F 00000100
+wait   %d200
+
+--rd 0000000000080000 F 00001234
+--wait   %d20
+--rd 0000000000080004 F 00005678
+--wait   %d20
+--rd 0000000000080008 F 0000abcd
+--wait   %d20
+--rd 000000000008000C F 0000ef90
+--wait   %d60
+--
+--wr 00000000000800FC F 00000001
+--wait   %d100
+--wr 00000000000800FC F 00000002
+--wait   %d100
+
+
+
+
+
+---- Gonzalo: registers inside Matthieu's core memory space are written with the
+---- settings for DMA transfer
+--
+---- Start address on the carrier local memory
+--wr 0000000000000008 F 00000000
+--wait   %d20
+--
+---- Start addresses on the PCI host memory
+--wr 000000000000000C F 0000A0A4
+--wait   %d20
+--wr 0000000000000010 F 0000A0A5
+--wait   %d20
+--
+---- Transfer length
+--wr 0000000000000014 F 00000060
+--wait   %d20
+--
+---- Chain control
+--wr 0000000000000020 F 00000000
+--wait   %d60
+--
+---- Start transfer through the Control register and check through the status register
+--wr 0000000000000000 F 00000001
+--wait   %d100
+--rd 0000000000000004 F 00000001
+--wait   %d100
+--
+--
--- a/hdl/sim/spec/data_vectors/memo_test_cmd0.vec
+++ b/hdl/sim/spec/data_vectors/memo_test_cmd0.vec
+-------------------------------------------------------------------------------
+-- acam_test.vec
+-------------------------------------------------------------------------------
+-- Select the GN4124 Primary BFM
+model 0
+
+-- Initialize the BFM to its default state
+init
+
+-------------------------------------------------------------------------------
+-- Initialize the Primary GN412x BFM model
+-------------------------------------------------------------------------------
+-- These address ranges will generate traffic from the BFM to the FPGA
+-- bar BAR ADDR SIZE VC TC S
+bar     0 0000000000000000 00100000 0 7 0
+
+-- This allocates a RAM block inside the BFM for the FPGA to access
+-- bfm_bar BAR ADDR SIZE
+bfm_bar 0 0000000040000000 20000000
+bfm_bar 1 0000000020000000 20000000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d50000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d60000
+
+-------------------------------------------------------------------------------
+-- Access the tdc core register space
+-------------------------------------------------------------------------------
+-- the following writes will go out in a single packet
+
+-- Gonzalo: 3 writings outside of the BAR defined memory space to check that 
+-- the BFM model does not forward them to the Local bus
+
+wr 0000000040000808 F 0001F04C
+wait   %d20
+wr 0000000040000800 F 00021040
+wait   %d20
+wr 0000000040000800 F 00025000
+wait   %d60
+
+-- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
+-- does not forward them to the wishbone bus
+
+rd 0000000000000000 F 0000A0A1
+wait   %d20
+rd 0000000000000004 F 0000A0A2
+wait   %d20
+rd 0000000000000008 F 0000A0A3
+wait   %d60
+
+-- Gonzalo: actual wr and rd on the application memory space for test
+
+wr 0000000000080000 F 00001234
+wait   %d20
+wr 0000000000080004 F 00005678
+wait   %d20
+wr 0000000000080008 F 0000abcd
+wait   %d20
+wr 000000000008000C F 0000ef90
+wait   %d60
+
+rd 0000000000080000 F 00001234
+wait   %d20
+rd 0000000000080004 F 00005678
+wait   %d20
+rd 0000000000080008 F 0000abcd
+wait   %d20
+rd 000000000008000C F 0000ef90
+wait   %d60
+
+wr 0000000000080100 F 00000001
+wait   %d100
+wr 0000000000080100 F 00000002
+wait   %d100
+
+-- Gonzalo: registers inside Matthieu's core memory space are written with the
+-- settings for DMA transfer
+
+-- Start address on the carrier local memory
+wr 0000000000000008 F 00000000
+wait   %d20
+
+-- Start addresses on the PCI host memory
+wr 000000000000000C F 0000A0A4
+wait   %d20
+wr 0000000000000010 F 0000A0A5
+wait   %d20
+
+-- Transfer length
+wr 0000000000000014 F 00000060
+wait   %d20
+
+-- Chain control
+wr 0000000000000020 F 00000000
+wait   %d60
+
+-- Start transfer through the Control register and check through the status register
+wr 0000000000000000 F 00000001
+wait   %d100
+rd 0000000000000004 F 00000001
+wait   %d100
+
--- a/hdl/sim/spec/data_vectors/pulses.txt
+++ b/hdl/sim/spec/data_vectors/pulses.txt
+2600 us  1  5 us
+800 us   2  505 ns
+162 ps   3  505 ns
+500 us   4   505 ns
+400 ps   1  505 ns
+18 ps   5   505 ns
+600 ns   1   100 ps
+110 ps   2   100 ps
+110 ps   3   100 ps
\ No newline at end of file
--- a/hdl/sim/spec/spec_fmc_tdc_sim.xise
+++ b/hdl/sim/spec/spec_fmc_tdc_sim.xise
--- a/hdl/testbench/spec/tb_tdc.vhd
+++ b/hdl/testbench/spec/tb_tdc.vhd
@@ -30,7 +30,7 @@ architecture behavioral of tb_tdc is
    generic(
        g_span                  : integer :=32;
        g_width                 : integer :=32;
-        values_for_simulation   : boolean :=FALSE
+        values_for_simul   : boolean :=FALSE
    );
    port(
        -- interface with GNUM circuit
@@ -58,12 +58,12 @@ architecture behavioral of tb_tdc is
        p_rd_d_rdy_i: in  std_logic_vector(1 downto 0);   -- PCIe-to-Local Read Response Data Ready
        tx_error_i  : in  std_logic;                      -- Transmit Error
        irq_p_o     : out std_logic;                      -- Interrupt request pulse to GN4124 GPIO
-        spare_o     : out std_logic;

       -- interface signals with PLL circuit
-        acam_refclk_i           : in std_logic;
-        pll_ld_i                : in std_logic;
-        pll_refmon_i            : in std_logic;
+        acam_refclk_p_i           : in std_logic;
+        acam_refclk_n_i           : in std_logic;
+        --pll_ld_i                : in std_logic;
+        --pll_refmon_i            : in std_logic;
        pll_sdo_i               : in std_logic;
        pll_status_i            : in std_logic;
        
@@ -86,8 +86,8 @@ architecture behavioral of tb_tdc is
        data_bus_io             : inout std_logic_vector(27 downto 0);
        ef1_i                   : in std_logic;
        ef2_i                   : in std_logic;
-        lf1_i                   : in std_logic;
-        lf2_i                   : in std_logic;
+        --lf1_i                   : in std_logic;
+        --lf2_i                   : in std_logic;

        address_o               : out std_logic_vector(3 downto 0);
        cs_n_o                  : out std_logic;
@@ -96,16 +96,28 @@ architecture behavioral of tb_tdc is
        wr_n_o                  : out std_logic;

        -- other signals on the tdc card
+        tdc_in_fpga_1_i         : in std_logic;
+        tdc_in_fpga_2_i         : in std_logic;
+        tdc_in_fpga_3_i         : in std_logic;
+        tdc_in_fpga_4_i         : in std_logic;
        tdc_in_fpga_5_i         : in std_logic;

-        mute_inputs_o           : out std_logic;
+
+        enable_inputs_o           : out std_logic;
        tdc_led_status_o        : out std_logic;
        tdc_led_trig1_o         : out std_logic;
        tdc_led_trig2_o         : out std_logic;
        tdc_led_trig3_o         : out std_logic;
        tdc_led_trig4_o         : out std_logic;
        tdc_led_trig5_o         : out std_logic;
-        
+
+        carrier_one_wire_b      : inout std_logic;
+        sys_scl_b               : inout std_logic;
+        sys_sda_b               : inout std_logic;
+        mezz_one_wire_b         : inout std_logic;
+        pcb_ver_i               : in std_logic_vector(3 downto 0);
+        prsnt_m2c_n_i           : in std_logic;
+
        -- other signals on the spec card
        spec_aux0_i             : in std_logic;
        spec_aux1_i             : in std_logic;
@@ -283,7 +295,8 @@ constant start_retrig_period    : time:= 512 ns;
  -- Maximum width of a command string
  constant STRING_MAX : integer                      := 256;

-signal acam_refclk_i        : std_logic:='0';
+signal acam_refclk_i        : std_logic:='0';
+signal acam_refclk_n_i      : std_logic:='1';
 signal tdc_clk_p_i          : std_logic:='0';
 signal tdc_clk_n_i          : std_logic:='1';
 signal spec_clk_i           : std_logic:='0';
@@ -389,7 +402,7 @@ begin
    generic map(
        g_span                  => 32,
        g_width                 => 32,
-        values_for_simulation   => TRUE
+        values_for_simul   => TRUE
    )
    port map(
        -- interface with GNUM circuit
@@ -415,12 +428,12 @@ begin
        p_rd_d_rdy_i            => p_rd_d_rdy,
        tx_error_i              => tx_error,
        irq_p_o                 => irq_p,
-        spare_o                 => spare,
        
        -- interface with PLL circuit
-        acam_refclk_i           => acam_refclk_i,
-        pll_ld_i                => pll_ld_i,
-        pll_refmon_i            => pll_refmon_i,
+        acam_refclk_p_i         => acam_refclk_i,
+        acam_refclk_n_i         => acam_refclk_n_i,
+        --pll_ld_i                => pll_ld_i,
+        --pll_refmon_i            => pll_refmon_i,
        pll_sdo_i               => pll_sdo_i,
        pll_status_i            => pll_status_i,
        
@@ -443,8 +456,8 @@ begin
        data_bus_io         => data_bus_io,
        ef1_i               => ef1_i,
        ef2_i               => ef2_i,
-        lf1_i               => lf1_i,
-        lf2_i               => lf2_i,
+        --lf1_i               => lf1_i,
+        --lf2_i               => lf2_i,
        
        address_o           => address_o,
        cs_n_o              => cs_n_o,
@@ -454,16 +467,27 @@ begin
        
        -- other signals on the tdc card
        tdc_in_fpga_5_i     => tdc_in_fpga_5,
-
-        mute_inputs_o       => mute_inputs,
+        tdc_in_fpga_1_i     => '0',
+        tdc_in_fpga_2_i     => '0',
+        tdc_in_fpga_3_i     => '0',
+        tdc_in_fpga_4_i     => '0',
+        enable_inputs_o     => mute_inputs,
        tdc_led_status_o    => tdc_led_status,
        tdc_led_trig1_o     => tdc_led_trig1,
        tdc_led_trig2_o     => tdc_led_trig2,
        tdc_led_trig3_o     => tdc_led_trig3,
        tdc_led_trig4_o     => tdc_led_trig4,
        tdc_led_trig5_o     => tdc_led_trig5,
-        
+
+
+       
        -- other signals on the spec card
+        carrier_one_wire_b  => open,
+        sys_scl_b           => open,
+        sys_sda_b           => open,
+        mezz_one_wire_b     => open,
+        pcb_ver_i           => (others => '0'),
+        prsnt_m2c_n_i       => '0',
        spec_aux0_i         => spec_aux0_i,
        spec_aux1_i         => spec_aux1_i,
        spec_aux2_o         => spec_aux2_o,
@@ -627,6 +651,9 @@ begin
        if pll_cs_o ='1' and rst_n ='1' then
            tdc_clk_p_i         <= not (tdc_clk_p_i) after 1 ns;
            tdc_clk_n_i         <= not (tdc_clk_n_i) after 1 ns;
+
+            pll_status_i        <= '1';
+
        end if;
        wait for pll_clk_period/2;
    end process;
@@ -638,6 +665,8 @@ begin
        end if;
        wait for pll_clk_period*2;
    end process;
+    acam_refclk_n_i <= not acam_refclk_i;
+
    
    spec_clock: process
    begin