Maintenance scheduled 24th July -- expect downtime along that day

Commit 4af69194 authored by penacoba's avatar penacoba

Generated circular buffer with RAM block.


git-svn-id: http://svn.ohwr.org/fmc-tdc@46 85dfdc96-de2c-444c-878d-45b388be74a9
parent 07fa5b23
----------------------------------------------------------------------------------------------------
-- CERN-BE-CO-HT
----------------------------------------------------------------------------------------------------
--
-- unit name : RAM circular buffer for timestamp storage (circular_buffer)
-- author : G. Penacoba
-- date : Oct 2011
-- version : Revision 1
-- description : contains the RAM block (512 x 32) and the wishbone slave interfaces.
-- From the side of the timestamps coming from the ACAM the wishbone interface is
-- classic. On the side of the DMA access from the PCI, the wishbone interface is
-- pipelined.
-- dependencies:
-- references :
-- modified by :
--
----------------------------------------------------------------------------------------------------
-- last changes:
----------------------------------------------------------------------------------------------------
-- to do:
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
----------------------------------------------------------------------------------------------------
-- entity declaration for circular_buffer
----------------------------------------------------------------------------------------------------
entity circular_buffer is
generic(
g_width : integer :=32
);
port(
-- wishbone classic slave signals to interface RAM with the internal modules providing the timestamps
class_clk_i : in std_logic;
class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(19 downto 0);
class_cyc_i : in std_logic;
class_dat_i : in std_logic_vector(4*g_width-1 downto 0);
class_stb_i : in std_logic;
class_we_i : in std_logic;
class_ack_o : out std_logic;
class_dat_o : out std_logic_vector(4*g_width-1 downto 0);
-- wishbone pipelined slave signals to interface RAM with gnum core for DMA access from PCI-e
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(19 downto 0);
pipe_cyc_i : in std_logic;
pipe_dat_i : in std_logic_vector(g_width-1 downto 0);
pipe_stb_i : in std_logic;
pipe_we_i : in std_logic;
pipe_ack_o : out std_logic;
pipe_dat_o : out std_logic_vector(g_width-1 downto 0);
pipe_stall_o : out std_logic
);
end circular_buffer;
----------------------------------------------------------------------------------------------------
-- architecture declaration for circular_buffer
----------------------------------------------------------------------------------------------------
architecture rtl of circular_buffer is
component blk_mem_gen_v6_2
port(
clka : in std_logic;
addra : in std_logic_vector(6 downto 0);
dina : in std_logic_vector(127 downto 0);
wea : in std_logic_vector(0 downto 0);
douta : out std_logic_vector(127 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(8 downto 0);
dinb : in std_logic_vector(31 downto 0);
web : in std_logic_vector(0 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component;
type t_wb_classic_mem_interface is (idle, acknowledge);
type t_wb_pipelined_mem_interface is (idle, mem_access, mem_access_and_acknowledge, acknowledge);
signal wb_classic_st, nxt_wb_classic_st : t_wb_classic_mem_interface;
signal wb_pipelined_st, nxt_wb_pipelined_st : t_wb_pipelined_mem_interface;
signal class_ack : std_logic;
signal class_adr : std_logic_vector(6 downto 0);
signal class_clk : std_logic;
signal class_cyc : std_logic;
signal class_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal class_data_wr : std_logic_vector(4*g_width-1 downto 0);
signal class_reset : std_logic;
signal class_stb : std_logic;
signal class_we : std_logic_vector(0 downto 0);
signal pipe_ack : std_logic;
signal pipe_adr : std_logic_vector(8 downto 0);
signal pipe_clk : std_logic;
signal pipe_cyc : std_logic;
signal pipe_data_rd : std_logic_vector(g_width-1 downto 0);
signal pipe_data_wr : std_logic_vector(g_width-1 downto 0);
signal pipe_reset : std_logic;
signal pipe_stb : std_logic;
signal pipe_we : std_logic_vector(0 downto 0);
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
begin
-- classic_seq_fsm: process
-- begin
-- if class_reset ='1' then
-- wb_classic_st <= idle;
-- else
-- wb_classic_st <= nxt_wb_classic_st;
-- end if;
-- wait until class_clk ='1';
-- end process;
--
-- classic_comb_fsm: process(wb_classic_st, class_stb, class_cyc)
-- begin
-- case wb_classic_st is
-- when idle =>
-- class_ack <= '0';
--
-- if class_stb ='1' and class_cyc ='1' then
-- nxt_wb_classic_st <= acknowledge;
-- else
-- nxt_wb_classic_st <= idle;
-- end if;
--
-- when acknowledge =>
-- class_ack <= '1';
--
-- nxt_wb_classic_st <= idle;
--
-- when others =>
-- class_ack <= '0';
--
-- nxt_wb_classic_st <= idle;
-- end case;
-- end process;
wishbone_classic_compatible_interface: process
begin
if class_reset ='1' then
class_ack <= '0';
else
class_ack <= class_stb and class_cyc;
end if;
wait until class_clk ='1';
end process;
pipelined_seq_fsm: process
begin
if pipe_reset ='1' then
wb_pipelined_st <= idle;
else
wb_pipelined_st <= nxt_wb_pipelined_st;
end if;
wait until pipe_clk ='1';
end process;
pipelined_comb_fsm: process(wb_pipelined_st, pipe_stb, pipe_cyc)
begin
case wb_pipelined_st is
when idle =>
pipe_ack <= '0';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access;
else
nxt_wb_pipelined_st <= idle;
end if;
when mem_access =>
pipe_ack <= '0';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access_and_acknowledge;
else
nxt_wb_pipelined_st <= acknowledge;
end if;
when mem_access_and_acknowledge =>
pipe_ack <= '1';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access_and_acknowledge;
else
nxt_wb_pipelined_st <= acknowledge;
end if;
when acknowledge =>
pipe_ack <= '1';
if pipe_stb ='1' and pipe_cyc ='1' then
nxt_wb_pipelined_st <= mem_access;
else
nxt_wb_pipelined_st <= idle;
end if;
when others =>
pipe_ack <= '0';
nxt_wb_pipelined_st <= idle;
end case;
end process;
memory_block: blk_mem_gen_v6_2
port map(
clka => class_clk,
addra => class_adr,
dina => class_data_wr,
wea => class_we,
douta => class_data_rd,
clkb => pipe_clk,
addrb => pipe_adr,
dinb => pipe_data_wr,
web => pipe_we,
doutb => pipe_data_rd
);
-- inputs from other blocks
class_clk <= class_clk_i;
class_reset <= class_reset_i;
class_adr <= class_adr_i(6 downto 0);
class_cyc <= class_cyc_i;
class_data_wr <= class_dat_i;
class_stb <= class_stb_i;
class_we(0) <= class_we_i;
pipe_clk <= pipe_clk_i;
pipe_reset <= pipe_reset_i;
pipe_adr <= pipe_adr_i(8 downto 0);
pipe_cyc <= pipe_cyc_i;
pipe_data_wr <= pipe_dat_i;
pipe_stb <= pipe_stb_i;
pipe_we(0) <= pipe_we_i;
-- outputs to other blocks
class_ack_o <= class_ack;
class_dat_o <= class_data_rd;
pipe_ack_o <= pipe_ack;
pipe_dat_o <= pipe_data_rd;
pipe_stall_o <= '0';
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
......@@ -235,6 +235,40 @@ architecture rtl of top_tdc is
);
end component;
component circular_buffer
generic(
g_width : integer :=32
);
port(
-- wishbone classic slave signals to interface RAM with the modules providing the timestamps
class_clk_i : in std_logic;
class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(19 downto 0);
class_cyc_i : in std_logic;
class_dat_i : in std_logic_vector(4*g_width-1 downto 0);
class_stb_i : in std_logic;
class_we_i : in std_logic;
class_ack_o : out std_logic;
class_dat_o : out std_logic_vector(4*g_width-1 downto 0);
-- wishbone pipelined slave signals to interface RAM with gnum core for DMA access from PCI-e
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(19 downto 0);
pipe_cyc_i : in std_logic;
pipe_dat_i : in std_logic_vector(g_width-1 downto 0);
pipe_stb_i : in std_logic;
pipe_we_i : in std_logic;
pipe_ack_o : out std_logic;
pipe_dat_o : out std_logic_vector(g_width-1 downto 0);
pipe_stall_o : out std_logic
);
end component;
component clk_rst_managr
generic(
nb_of_reg : integer:=68;
......@@ -419,13 +453,27 @@ signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_ack : std_logic;
signal dma_stall : std_logic;
signal mem_class_adr : std_logic_vector(19 downto 0);
signal mem_class_cyc : std_logic;
signal mem_class_data_wr : std_logic_vector(4*g_width-1 downto 0);
signal mem_class_stb : std_logic;
signal mem_class_we : std_logic;
signal mem_class_ack : std_logic;
signal mem_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal mem_pipe_adr : std_logic_vector(19 downto 0);
signal mem_pipe_cyc : std_logic;
signal mem_pipe_data_wr : std_logic_vector(g_width-1 downto 0);
signal mem_pipe_stb : std_logic;
signal mem_pipe_we : std_logic;
signal mem_pipe_ack : std_logic;
signal mem_pipe_data_rd : std_logic_vector(g_width-1 downto 0);
signal mem_pipe_stall : std_logic;
signal acam_refclk : std_logic;
signal clk : std_logic;
signal spec_clk : std_logic;
signal conditions_reg : unsigned(2 downto 0);
signal conditions_pulse : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
......@@ -536,6 +584,39 @@ begin
dat_o => acm_dat_r
);
circular_buffer_block: circular_buffer
generic map(
g_width => g_width
)
port map(
-- wishbone classic slave signals to interface RAM with the internal modules providing the timestamps
class_clk_i => clk,
class_reset_i => general_reset,
class_adr_i => mem_class_adr,
class_cyc_i => mem_class_cyc,
class_dat_i => mem_class_data_wr,
class_stb_i => mem_class_stb,
class_we_i => mem_class_we,
class_ack_o => mem_class_ack,
class_dat_o => mem_class_data_rd,
-- wishbone pipelined slave signals to interface RAM with gnum core for DMA access from PCI-e
pipe_clk_i => clk,
pipe_reset_i => general_reset,
pipe_adr_i => mem_pipe_adr,
pipe_cyc_i => mem_pipe_cyc,
pipe_dat_i => mem_pipe_data_wr,
pipe_stb_i => mem_pipe_stb,
pipe_we_i => mem_pipe_we,
pipe_ack_o => mem_pipe_ack,
pipe_dat_o => mem_pipe_data_rd,
pipe_stall_o => mem_pipe_stall
);
gnum_interface_block: gn4124_core
generic map(
g_CSR_WB_SLAVES_NB => 1
......@@ -687,14 +768,30 @@ begin
-- internal signals
spec_led_green <= pll_ld_i;
acm_adr(19) <= '0';
acm_adr(18 downto 0) <= csr_adr;
acm_cyc <= csr_cyc(0);
acm_stb <= csr_stb;
acm_we <= csr_we;
acm_dat_w <= csr_dat_w;
csr_ack(0) <= acm_ack;
csr_dat_r <= acm_dat_r;
-- acm_adr(19) <= '0';
-- acm_adr(18 downto 0) <= csr_adr;
-- acm_cyc <= csr_cyc(0);
-- acm_stb <= csr_stb;
-- acm_we <= csr_we;
-- acm_dat_w <= csr_dat_w;
-- csr_ack(0) <= acm_ack;
-- csr_dat_r <= acm_dat_r;
mem_class_adr(19) <= '0';
mem_class_adr(18 downto 0) <= csr_adr;
mem_class_cyc <= csr_cyc(0);
mem_class_stb <= csr_stb;
mem_class_we <= csr_we;
mem_class_data_wr(127 downto 32) <= (others=>'0');
mem_class_data_wr(31 downto 0) <= csr_dat_w;
csr_ack(0) <= mem_class_ack;
csr_dat_r <= mem_class_data_rd(31 downto 0);
mem_pipe_adr <= (others=>'0');
mem_pipe_cyc <= '0';
mem_pipe_stb <= '0';
mem_pipe_we <= '0';
mem_pipe_data_wr <= (others=>'0');
-- inputs
-- gnum_reset <= not(rst_n_a_i) or not(spec_aux1_i);
......
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