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FMC TDC 1ns 5cha - Gateware
Commit 512fe0df authored by egousiou's avatar egousiou
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folders restructuring; one core for both spec and svec 

git-svn-id: http://svn.ohwr.org/fmc-tdc@124 85dfdc96-de2c-444c-878d-45b388be74a9
parent 4d5b3487
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hdl/spec/sim/.nclaunch.dd deleted 100644 → 0
View file @ 4d5b3487
# DO NOT EDIT -- automatically generated design data file -- DO NOT EDIT!!!
list \
workdir {/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim} \
cdslib {/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/cds.lib} \
worklib {worklib} \
mode {0} \
filters {*} \
sesslist {} \
ToolOption_NCVhdl {-logfile ncvhdl.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/AMS {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/SV {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_irun {-gui {} +linedebug +access rwc -q} \
ToolOption_NCElab {-logfile ncelab.log -errormax 15 -status -access +wc} \
ToolOption_NCSim {-gui -logfile ncsim.log -errormax 15 -status} \
ToolOption_NCSdfc {-logfile ncsdfc.log -compile -status} \
ToolOption_HAL {-logfile hal.log} \
ToolOption_SimVision {} \
ToolOption_Update {-errormax 15 -force} \
ToolOption_Comparescan {} \
ToolOption_NCBrowse {} \
ToolOption_HALDefEdit {} \
ToolOption_PLI Wizard {} \
ToolOption_NCShell {-view shell -logfile ncshell.log -errormax 15 -suffix .v} \
ToolOption_NCProtect {-logfile ncprotect.log} \
ToolOption_NCDC {-logfile ncdc.log -messages -status} \
ToolOption_DBUtil {} \
ToolOption_NCVhdl {-logfile ncvhdl.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/AMS {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/SV {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_irun {-gui {} +linedebug +access rwc -q} \
ToolOption_NCElab {-logfile ncelab.log -errormax 15 -status -access +wc} \
ToolOption_NCSim {-gui -logfile ncsim.log -errormax 15 -status} \
ToolOption_NCSdfc {-logfile ncsdfc.log -compile -status} \
ToolOption_HAL {-logfile hal.log} \
ToolOption_SimVision {} \
ToolOption_Update {-errormax 15 -force} \
ToolOption_Comparescan {} \
ToolOption_NCBrowse {} \
ToolOption_HALDefEdit {} \
ToolOption_PLI Wizard {} \
ToolOption_NCShell {-view shell -logfile ncshell.log -errormax 15 -suffix .v} \
ToolOption_NCProtect {-logfile ncprotect.log} \
ToolOption_NCDC {-logfile ncdc.log -messages -status} \
ToolOption_DBUtil {} \
hdl/spec/sim/.nclaunch.dd.bak deleted 100644 → 0
View file @ 4d5b3487
# DO NOT EDIT -- automatically generated design data file -- DO NOT EDIT!!!
list \
workdir {/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim} \
cdslib {/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/cds.lib} \
worklib {worklib} \
mode {0} \
filters {*} \
sesslist {} \
ToolOption_NCVhdl {-logfile ncvhdl.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/AMS {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/SV {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_irun {-gui {} +linedebug +access rwc -q} \
ToolOption_NCElab {-logfile ncelab.log -errormax 15 -status -access +wc} \
ToolOption_NCSim {-gui -logfile ncsim.log -errormax 15 -status} \
ToolOption_NCSdfc {-logfile ncsdfc.log -compile -status} \
ToolOption_HAL {-logfile hal.log} \
ToolOption_SimVision {} \
ToolOption_Update {-errormax 15 -force} \
ToolOption_Comparescan {} \
ToolOption_NCBrowse {} \
ToolOption_HALDefEdit {} \
ToolOption_PLI Wizard {} \
ToolOption_NCShell {-view shell -logfile ncshell.log -errormax 15 -suffix .v} \
ToolOption_NCProtect {-logfile ncprotect.log} \
ToolOption_NCDC {-logfile ncdc.log -messages -status} \
ToolOption_DBUtil {} \
ToolOption_NCVhdl {-logfile ncvhdl.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/AMS {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/SV {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_irun {-gui {} +linedebug +access rwc -q} \
ToolOption_NCElab {-logfile ncelab.log -errormax 15 -status -access +wc} \
ToolOption_NCSim {-gui -logfile ncsim.log -errormax 15 -status} \
ToolOption_NCSdfc {-logfile ncsdfc.log -compile -status} \
ToolOption_HAL {-logfile hal.log} \
ToolOption_SimVision {} \
ToolOption_Update {-errormax 15 -force} \
ToolOption_Comparescan {} \
ToolOption_NCBrowse {} \
ToolOption_HALDefEdit {} \
ToolOption_PLI Wizard {} \
ToolOption_NCShell {-view shell -logfile ncshell.log -errormax 15 -suffix .v} \
ToolOption_NCProtect {-logfile ncprotect.log} \
ToolOption_NCDC {-logfile ncdc.log -messages -status} \
ToolOption_DBUtil {} \
hdl/spec/sim/cds.lib deleted 100644 → 0
View file @ 4d5b3487
include $CDS_INST_DIR/tools/inca/files/cds.lib
define worklib /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/worklib
DEFINE secureip /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/secureip
DEFINE unimacro /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/unimacro
DEFINE unisim /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/unisim
DEFINE xilinxcorelib /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/xilinxcorelib
hdl/spec/sim/data_vectors/acam_test_cmd0.vec deleted 100644 → 0
View file @ 4d5b3487
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
-- Gonzalo: 3 writings outside of the BAR defined memory space to check that
-- the BFM model does not forward them to the Local bus
wr 0000000040000808 F 0001F04C
wait %d50
wr 0000000040000800 F 00021040
wait %d50
wr 0000000040000800 F 00025000
wait %d50
-- Gonzalo: 5 reads inside Matthieu's core memory space to check that the core
-- does not forward them to the wishbone bus
rd 0000000000000000 F 0000A0A1
wait %d20
rd 0000000000000004 F 0000A0A2
wait %d20
rd 0000000000000008 F 0000A0A3
wait %d20
rd 000000000000000C F 0000A0A4
wait %d20
rd 0000000000000010 F 0000A0A5
wait %d60
-- Gonzalo: actual wr and rd for test
wr 0000000000080000 F 0000FC81
wait %d50
wr 000000000008002C F 00FF0000
wait %d50
rd 0000000000080000 F 0000FC81
wait %d50
rd 000000000008002C F 00FF0000
wait %d50
wr 0000000000080030 F 04000000
wait %d50
rd 0000000000080030 F 04000000
wait %d50
hdl/spec/sim/data_vectors/atdc_test_cmd0.vec deleted 100644 → 0
View file @ 4d5b3487
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
---- Gonzalo: 3 writings outside of the BAR defined memory space to check that
---- the BFM model does not forward them to the Local bus
--wr 0000000040000808 F 0001F04C
--wait %d20
--wr 0000000040000800 F 00021040
--wait %d20
--wr 0000000040000800 F 00025000
--wait %d60
---- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
---- does not forward them to the wishbone bus
--rd 0000000000000000 F 0000A0A1
--wait %d20
--rd 0000000000000004 F 0000A0A2
--wait %d20
--rd 0000000000000008 F 0000A0A3
--wait %d60
-- Gonzalo: actual wr and rd on the application memory space for test
-- writing stuff on the TDC config
wr 0000000000080080 F 00000040
wait %d20
wr 0000000000080084 F 00000000
wait %d20
wr 0000000000080088 F 00000000
wait %d60
-- writing stuff for the ACAM config
wr 0000000000080000 F 01F0FC81
wait %d20
wr 0000000000080004 F 00000000
wait %d20
wr 0000000000080008 F 00000E02
wait %d60
-- loading the utc time
wr 00000000000800FC F 00000200
wait %d200
-- loading the acam config
wr 00000000000800FC F 00000004
wait %d200
-- reading back the acam config
wr 00000000000800FC F 00000008
wait %d200
-- activate acquisition
wr 00000000000800FC F 00000001
wait %d540000
-- read circular buffer wr pointer
rd 000000000008009C F 00000000
wait %d200
-- prepare and launch DMA transfer
wr 000000000000000C F 36EF8000
wait %d20
wr 0000000000000014 F 00000210
wait %d100
wr 0000000000000000 F 00000001
wait %d100
-- deactivate acquisition
wr 00000000000800FC F 00000002
wait %d200
-- read acam status
wr 00000000000800FC F 00000010
wait %d100
rd 0000000000080070 F 00000000
wait %d100
-- read acam ififo1
wr 00000000000800FC F 00000020
wait %d100
rd 0000000000080060 F 00000000
wait %d100
-- read acam ififo2
wr 00000000000800FC F 00000040
wait %d100
rd 0000000000080064 F 00000000
wait %d100
-- read acam start01 register
wr 00000000000800FC F 00000080
wait %d100
rd 0000000000080068 F 00000000
wait %d100
-- reset acam
wr 00000000000800FC F 00000100
wait %d200
--rd 0000000000080000 F 00001234
--wait %d20
--rd 0000000000080004 F 00005678
--wait %d20
--rd 0000000000080008 F 0000abcd
--wait %d20
--rd 000000000008000C F 0000ef90
--wait %d60
--
--wr 00000000000800FC F 00000001
--wait %d100
--wr 00000000000800FC F 00000002
--wait %d100
---- Gonzalo: registers inside Matthieu's core memory space are written with the
---- settings for DMA transfer
--
---- Start address on the carrier local memory
--wr 0000000000000008 F 00000000
--wait %d20
--
---- Start addresses on the PCI host memory
--wr 000000000000000C F 0000A0A4
--wait %d20
--wr 0000000000000010 F 0000A0A5
--wait %d20
--
---- Transfer length
--wr 0000000000000014 F 00000060
--wait %d20
--
---- Chain control
--wr 0000000000000020 F 00000000
--wait %d60
--
---- Start transfer through the Control register and check through the status register
--wr 0000000000000000 F 00000001
--wait %d100
--rd 0000000000000004 F 00000001
--wait %d100
--
--
hdl/spec/sim/data_vectors/memo_test_cmd0.vec deleted 100644 → 0
View file @ 4d5b3487
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d60000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
-- Gonzalo: 3 writings outside of the BAR defined memory space to check that
-- the BFM model does not forward them to the Local bus
wr 0000000040000808 F 0001F04C
wait %d20
wr 0000000040000800 F 00021040
wait %d20
wr 0000000040000800 F 00025000
wait %d60
-- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
-- does not forward them to the wishbone bus
rd 0000000000000000 F 0000A0A1
wait %d20
rd 0000000000000004 F 0000A0A2
wait %d20
rd 0000000000000008 F 0000A0A3
wait %d60
-- Gonzalo: actual wr and rd on the application memory space for test
wr 0000000000080000 F 00001234
wait %d20
wr 0000000000080004 F 00005678
wait %d20
wr 0000000000080008 F 0000abcd
wait %d20
wr 000000000008000C F 0000ef90
wait %d60
rd 0000000000080000 F 00001234
wait %d20
rd 0000000000080004 F 00005678
wait %d20
rd 0000000000080008 F 0000abcd
wait %d20
rd 000000000008000C F 0000ef90
wait %d60
wr 0000000000080100 F 00000001
wait %d100
wr 0000000000080100 F 00000002
wait %d100
-- Gonzalo: registers inside Matthieu's core memory space are written with the
-- settings for DMA transfer
-- Start address on the carrier local memory
wr 0000000000000008 F 00000000
wait %d20
-- Start addresses on the PCI host memory
wr 000000000000000C F 0000A0A4
wait %d20
wr 0000000000000010 F 0000A0A5
wait %d20
-- Transfer length
wr 0000000000000014 F 00000060
wait %d20
-- Chain control
wr 0000000000000020 F 00000000
wait %d60
-- Start transfer through the Control register and check through the status register
wr 0000000000000000 F 00000001
wait %d100
rd 0000000000000004 F 00000001
wait %d100
hdl/spec/sim/data_vectors/pulses.txt deleted 100644 → 0
View file @ 4d5b3487
2600 us,1,5 us
800 us,2,505 ns
162 ps,3,505 ns
500 us,4,505 ns
400 ps,1,505 ns
18 ps,5,505 ns
600 ns,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
hdl/spec/sim/hdl.var deleted 100644 → 0
View file @ 4d5b3487
define WORK worklib
include $CDS_INST_DIR/tools/inca/files/hdl.var
hdl/spec/sim/sim.tcl deleted 100644 → 0
View file @ 4d5b3487
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/l2p_ser_s6.vhd
ncvhdl -controlrelax NLSTEX -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/p2l_des_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/p2l_decode32.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/wbmaster32.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/dma_controller.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/l2p_dma_master.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/p2l_dma_master.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/l2p_arbiter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/gnum_core/gn4124_core_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/tdc_core_pkg.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/free_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/incr_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/countdown_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/clk_rst_managr.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/one_hz_gen.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/start_retrigger_control.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/data_formatting.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/data_engine.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/acam_timecontrol_interface.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/acam_databus_interface.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/ip_cores/mem_core/reg_mem_gen_v6_2.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/circular_buffer.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/reg_ctrl.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/data_engine.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/top_tdc.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/test_tdc_acam/top_test_acam.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/rtl/test_tdc_pll/top_test_pll.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/util.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/textutil.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/mem_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/cmd_router1.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/cmd_router.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/gn412x_bfm.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/acam_timing_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/acam_fifo_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/acam_data_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/acam_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/start_stop_gen.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/tb_tdc.vhd
ncelab -nocopyright -nolog -messages -access +wc -messages -v93 -cdslib ./cds.lib -work worklib worklib.tb_tdc:behavioral
#ncelab -nocopyright -nolog -messages -access +wc -messages -v93 -cdslib ./cds.lib -work worklib worklib.tdc_top:rtl
#ncsim -gui -cdslib ./cds.lib -nocopyright -nolog -nokey worklib.tb_tdc:behavioral -input waves.tcl
hdl/spec/sim/waves.tcl deleted 100644 → 0
View file @ 4d5b3487
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