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FMC TDC 1ns 5cha - Gateware
Commit 7b243fd4 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] [bugfix] Fix overflow/underflow check in timestamp adder/subtractor

parent 84ffc99f
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hdl/rtl/tdc_ts_addsub.vhd
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...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN -- Company : CERN
-- Created : 2011-08-29 -- Created : 2011-08-29
-- Last update: 2018-09-10 -- Last update: 2019-09-26
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -169,9 +169,9 @@ begin -- rtl ...@@ -169,9 +169,9 @@ begin -- rtl
unf_coarse <= "00"; unf_coarse <= "00";
end if; end if;
if ( sums(1).coarse >= g_frac_range ) then if ( sums(1).coarse >= g_coarse_range ) then
ovf_coarse <= "10"; ovf_coarse <= "10";
elsif ( sums(1).coarse >= 2*g_frac_range ) then elsif ( sums(1).coarse >= 2*g_coarse_range ) then
ovf_coarse <= "01"; ovf_coarse <= "01";
else else
ovf_coarse <= "00"; ovf_coarse <= "00";
......
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