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FMC TDC 1ns 5cha - Gateware
Commit 84739413 authored by egousiou's avatar egousiou
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changes for new version (v2) of TDC mezz 

git-svn-id: http://svn.ohwr.org/fmc-tdc@77 85dfdc96-de2c-444c-878d-45b388be74a9
parent d34e1405
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Showing with 195 additions and 230 deletions
hdl/spec/src/rtl/acam_databus_interface.vhd
View file @ 84739413
......@@ -24,7 +24,7 @@
-- | |___CSn_______| |___cyc______| | |
-- | ACAM |___OEn_______| acam_ |___we_______| data_ | |
-- | |___EF________| databus_ |___ack______| engine | |
-- | |___LF________| interface |___adr______| | |
-- | | | interface |___adr______| | |
-- | |___ADR_______| |___datI_____| | |
-- | |___DatabusIO_| |___datO_____| | |
-- |___________| |____________| |___________| |
......@@ -85,8 +85,6 @@ entity acam_databus_interface is
-- Signals from the ACAM chip
ef1_i : in std_logic; -- FIFO1 empty flag
ef2_i : in std_logic; -- FIFO1 empty flag
lf1_i : in std_logic; -- load flag, not used
lf2_i : in std_logic; -- load flag, not used
data_bus_io : inout std_logic_vector(27 downto 0);
......@@ -114,7 +112,7 @@ entity acam_databus_interface is
-- Signals to the data_engine unit
ack_o : out std_logic; -- WISHBONE ack
dat_o : out std_logic_vector(31 downto 0)); -- ef1 & ef2 & lf1 & lf2 & 28 bits acam data_bus_io
dat_o : out std_logic_vector(31 downto 0)); -- ef1 & ef2 & 0 & 0 & 28 bits acam data_bus_io
end acam_databus_interface;
......@@ -128,7 +126,7 @@ architecture rtl of acam_databus_interface is
type t_acam_interface is (IDLE, RD_START, RD_FETCH, RD_ACK, WR_START, WR_PUSH, WR_ACK);
signal acam_data_st, nxt_acam_data_st : t_acam_interface;
signal ef1_synch, ef2_synch, lf1_synch, lf2_synch : std_logic_vector(1 downto 0);
signal ef1_synch, ef2_synch : std_logic_vector(1 downto 0);
signal ack, cs, cs_extend, rd, rd_extend, wr, wr_extend, wr_remove : std_logic;
......@@ -148,13 +146,9 @@ begin
if rst_i ='1' then
ef1_synch <= (others =>'1');
ef2_synch <= (others =>'1');
lf1_synch <= (others =>'0');
lf2_synch <= (others =>'0');
else
ef1_synch <= ef1_i & ef1_synch(1);
ef2_synch <= ef2_i & ef2_synch(1);
lf1_synch <= lf1_i & lf1_synch(1);
lf2_synch <= lf2_i & lf2_synch(1);
end if;
end if;
end process;
......@@ -298,8 +292,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
ack_o <= ack;
-- to the 28 bits databus output we add the ef and lf flags to arrive to a 32 bits word
dat_o <= ef1_synch(0) & ef2_synch(0) & lf1_synch(0) & lf2_synch(0) & data_bus_io;
-- to the 28 bits databus output we add the ef flags to arrive to a 32 bits word
dat_o <= ef1_synch(0) & ef2_synch(0) & "00" & data_bus_io;
......
hdl/spec/src/rtl/acam_timecontrol_interface.vhd
View file @ 84739413
......@@ -184,7 +184,7 @@ begin
total_delay <= std_logic_vector(unsigned(window_delay_i)+constant_delay);
start_pulse_from_fpga: process (clk_i) -- start pulse in the middle of the
start_pulse_from_fpga: process (clk_i) -- start pulse in the middle of the
begin -- de-assertion window of StartDisable
if rising_edge (clk_i) then
if rst_i ='1' then
......@@ -201,7 +201,7 @@ begin
-- Synchronization of the activate_acq_p with the acam_refclk_i
-- Synchronization of the activate_acq_p with the acam_refclk_p_i
ready_to_trigger: process (clk_i)
begin
if rising_edge (clk_i) then
......@@ -220,7 +220,7 @@ begin
actual_trigger_received: process (clk_i) -- signal needed to exclude the generation of
actual_trigger_received: process (clk_i) -- signal needed to exclude the generation of
begin -- the start_from_fpga_o after a general rst_i
if rising_edge (clk_i) then
if rst_i ='1' then
......
hdl/spec/src/rtl/clks_rsts_manager.vhd
View file @ 84739413
......@@ -27,7 +27,7 @@
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.2 EG Added DFFs to the pll_sdi_o, pll_cs_o outputs |
-- Changed completely the internal reset generation; now it depends |
-- on the pll_ld activation |
-- on the pll_status activation |
-- General revamping, comments added, signals renamed |
-- 05/2012 v0.3 EG Added logic for DAC configuration |
-- |
......@@ -75,14 +75,13 @@ entity clks_rsts_manager is
(spec_clk_i : in std_logic; -- 20 MHz OSC on SPEC board
-- Clock signals from the PLL
acam_refclk_i : in std_logic; -- 31.25 MHz clock generated by the PLL, clock of ACAM
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock generated by the PLL, clock of ACAM
acam_refclk_n_i : in std_logic; -- 31.25 MHz clock generated by the PLL, clock of ACAM
tdc_clk_p_i : in std_logic; -- 125 MHz clock generated by the PLL, clock of all other TDC core logic
tdc_clk_n_i : in std_logic;
-- Other signals from the PLL
pll_ld_i : in std_logic; -- PLL lock detect
pll_refmon_i : in std_logic; -- not used
pll_status_i : in std_logic; -- not used
pll_status_i : in std_logic; -- PLL lock detect
pll_sdo_i : in std_logic; -- not used
-- Signal from the GNUM
......@@ -105,12 +104,12 @@ entity clks_rsts_manager is
pll_sclk_o : out std_logic; -- SPI clock
-- Signal to the one_hz_gen and acam_timecontrol_interface units
acam_refclk_r_edge_p_o : out std_logic; -- pulse upon acam_refclk_i rising edge
acam_refclk_r_edge_p_o : out std_logic; -- pulse upon acam_refclk_p_i rising edge
-- Signals to the leds_manager unit
gnum_rst_o : out std_logic; -- GENUM reset synched with 20 MHz clock
spec_clk_o : out std_logic; -- 20 MHz clock
pll_ld_o : out std_logic);-- PLL lock detect synched with 20 MHz clock
pll_status_o : out std_logic);-- PLL lock detect synched with 20 MHz clock
end clks_rsts_manager;
......@@ -142,7 +141,7 @@ architecture rtl of clks_rsts_manager is
constant REG_014 : t_byte := x"09";
constant REG_015 : t_byte := x"00";
constant REG_016 : t_byte := x"04";
constant REG_017 : t_byte := x"00";
constant REG_017 : t_byte := x"B4"; -- PLL_STATUS
constant REG_018 : t_byte := x"07";
constant REG_019 : t_byte := x"00";
constant REG_01A : t_byte := x"00";
......@@ -172,7 +171,7 @@ architecture rtl of clks_rsts_manager is
constant REG_0F4 : t_byte := x"0A";
constant REG_0F5 : t_byte := x"0A";
constant REG_140 : t_byte := x"4A";
constant REG_140 : t_byte := x"42"; -----REF_CLK
constant REG_141 : t_byte := x"5A";
constant REG_142 : t_byte := x"43";
constant REG_143 : t_byte := x"42";
......@@ -225,11 +224,11 @@ architecture rtl of clks_rsts_manager is
signal pll_byte_index : integer range nb_of_reg-1 downto 0;
signal pll_cs_n, dac_cs_n : std_logic;
-- Synchronizers
signal pll_ld_synch, internal_rst_synch, gnum_rst_synch : std_logic_vector (1 downto 0);
signal pll_status_synch, internal_rst_synch, gnum_rst_synch : std_logic_vector (1 downto 0);
signal acam_refclk_synch, send_dac_word_p_synch : std_logic_vector (2 downto 0);
-- Clock buffers
signal spec_clk_buf, tdc_clk_buf : std_logic;
signal sclk, spec_clk, tdc_clk : std_logic;
signal spec_clk_buf, tdc_clk_buf, acam_refclk_buf : std_logic;
signal sclk, spec_clk, tdc_clk, acam_refclk : std_logic;
-- Resets
signal rst, internal_rst, gnum_rst : std_logic;
......@@ -277,6 +276,22 @@ begin
-- -- -- -- -- -- -- --
spec_clk_o <= spec_clk;
---------------------------------------------------------------------------------------------------
acam_refclk31M25_ibuf : IBUFDS
generic map
(DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map
(O => acam_refclk,
I => acam_refclk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => acam_refclk_n_i);-- Diff_n buffer input (connect directly to top-level port)
--acam_refclk31M25_gbuf : BUFG
--port map
-- (O => acam_refclk,
-- I => acam_refclk_buf);
---------------------------------------------------------------------------------------------------
-- General Internal Reset --
......@@ -299,26 +314,26 @@ begin
gnum_rst_o <= gnum_rst_synch(1);
---------------------------------------------------------------------------------------------------
-- Synchronous process PLL_LD_synchronizer: Synchronization of the pll_ld_i input to the spec_clk,
-- using a set of 2 registers.
PLL_LD_synchronizer: process (spec_clk)
-- Synchronous process pll_status_synchronizer: Synchronization of the pll_status_i input to the
-- spec_clk, using a set of 2 registers.
pll_status_synchronizer: process (spec_clk)
begin
if rising_edge (spec_clk) then
if gnum_rst = '1' then
pll_ld_synch <= (others => '0');
pll_status_synch <= (others => '0');
else
pll_ld_synch <= pll_ld_synch(0) & pll_ld_i;
pll_status_synch <= pll_status_synch(0) & pll_status_i;
end if;
end if;
end process;
-- -- -- -- -- -- -- --
pll_ld_o <= pll_ld_synch(1);
pll_status_o <= pll_status_synch(1);
---------------------------------------------------------------------------------------------------
-- Synchronous process Internal_rst_generation: Generation of a reset signal for as long as the PLL
-- is not locked. As soon as the pll_ld is received the internal reset is released.
-- Note that the level of the pll_ld signal rather than its rising edge is used, as in the case of
-- a gnum_rst during operation with the pll already locked the pll_ld will remain active and no
-- is not locked. As soon as the pll_status is received the internal reset is released.
-- Note that the level of the pll_status signal rather than its rising edge is used, as in the case of
-- a gnum_rst during operation with the pll already locked the pll_status will remain active and no
-- edge will appear.
Internal_rst_generator: process (spec_clk)
begin
......@@ -326,7 +341,7 @@ begin
if gnum_rst = '1' then
rst <= '1';
else
if pll_ld_synch(1) = '1' then
if pll_status_synch(1) = '1' then
rst <= '0';
else
rst <= '1';
......@@ -358,7 +373,7 @@ begin
if internal_rst_synch(1) = '1' then
acam_refclk_synch <= (others => '0');
else
acam_refclk_synch <= acam_refclk_synch(1 downto 0) & acam_refclk_i;
acam_refclk_synch <= acam_refclk_synch(1 downto 0) & acam_refclk;
end if;
end if;
end process;
......
hdl/spec/src/rtl/data_engine.vhd
View file @ 84739413
......@@ -108,7 +108,7 @@ entity data_engine is
-- Signals from the acam_databus_interface unit: WISHBONE master
acam_ack_i : in std_logic; -- WISHBONE ack
acam_dat_i : in std_logic_vector(31 downto 0); -- tstamps or rdbk regs
-- includes ef1 & ef2 & lf1 & lf2 & 28 bits acam data_bus_io
-- includes ef1 & ef2 & 0 & 0 & 28 bits acam data_bus_io
-- OUTPUTS
......@@ -127,8 +127,8 @@ entity data_engine is
acam_start01_o : out std_logic_vector(31 downto 0);-- keeps value read from ACAM reg 10
-- Signals to the data_formatting unit:
acam_tstamp1_o : out std_logic_vector(31 downto 0);-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO1
acam_tstamp2_o : out std_logic_vector(31 downto 0);-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO2
acam_tstamp1_o : out std_logic_vector(31 downto 0);-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO1
acam_tstamp2_o : out std_logic_vector(31 downto 0);-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO2
acam_tstamp1_ok_p_o : out std_logic; -- indication of a valid tstamp1
acam_tstamp2_ok_p_o : out std_logic);-- indication of a valid tstamp2
......
hdl/spec/src/rtl/data_formatting.vhd
View file @ 84739413
......@@ -73,10 +73,10 @@ entity data_formatting is
-- Signals from the data_engine unit
acam_tstamp1_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO1
-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO1
acam_tstamp1_ok_p_i : in std_logic; -- tstamp2 valid indicator
acam_tstamp2_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
-- includes ef1 & ef2 & lf1 & lf2 & 28 bits tstamp from FIFO2
-- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO2
acam_tstamp2_ok_p_i : in std_logic; -- tstamp2 valid indicator
-- Signals from the reg_ctrl unit
......@@ -122,7 +122,7 @@ architecture rtl of data_formatting is
constant c_MULTIPLY_BY_SIXTEEN : std_logic_vector(3 downto 0) := x"0";
-- ACAM timestamp fields
signal acam_channel : std_logic_vector(2 downto 0);
signal acam_slope, acam_fifo_ef, acam_fifo_lf : std_logic;
signal acam_slope, acam_fifo_ef : std_logic;
signal acam_fine_timestamp : std_logic_vector(16 downto 0);
signal acam_start_nb : std_logic_vector(7 downto 0);
-- timestamp manipulations
......@@ -248,8 +248,8 @@ begin
-- [25:18] Start number /
-- [27:26] Channel Code /
-- [28] lf2 \
-- [29] lf1 \ empty and load flags (added by the acam_databus_interface unit)
-- [28] 0 \
-- [29] 0 \ empty and load flags (added by the acam_databus_interface unit)
-- [30] ef2 /
-- [31] ef1 /
......@@ -265,7 +265,7 @@ begin
-- [95:64] Local UTC time coming from the one_hz_generator;
-- each bit represents 1s
-- [127:96] Metadata for each timestamp: "00..00" & lf & ef & Slope & Channel
-- [127:96] Metadata for each timestamp: "00..00" & 0 & ef & Slope & Channel
tstamp_formatting: process (clk_i)
begin
......@@ -273,7 +273,6 @@ begin
if rst_i ='1' then
acam_channel <= (others => '0');
acam_fifo_ef <= '0';
acam_fifo_lf <= '0';
acam_fine_timestamp <= (others => '0');
acam_slope <= '0';
acam_start_nb <= (others => '0');
......@@ -281,7 +280,6 @@ begin
elsif acam_tstamp1_ok_p_i = '1' then
acam_channel <= "0" & acam_tstamp1_i(27 downto 26);
acam_fifo_ef <= acam_tstamp1_i(31);
acam_fifo_lf <= acam_tstamp1_i(29);
acam_fine_timestamp <= acam_tstamp1_i(16 downto 0);
acam_slope <= acam_tstamp1_i(17);
acam_start_nb <= acam_tstamp1_i(25 downto 18);
......@@ -289,7 +287,6 @@ begin
elsif acam_tstamp2_ok_p_i ='1' then
acam_channel <= "1" & acam_tstamp2_i(27 downto 26);
acam_fifo_ef <= acam_tstamp2_i(30);
acam_fifo_lf <= acam_tstamp2_i(28);
acam_fine_timestamp <= acam_tstamp2_i(16 downto 0);
acam_slope <= acam_tstamp2_i(17);
acam_start_nb <= acam_tstamp2_i(25 downto 18);
......
hdl/spec/src/rtl/leds_manager.vhd
View file @ 84739413
......@@ -33,7 +33,7 @@
-- TDC LED 4 orange: Channel 3 terminatio enable |
-- TDC LED 5 orange: Channel 4 terminatio enable |
-- TDC LED 6 orange: Channel 5 terminatio enable |
-- SPEC LED 1 green : PLL lock detect |
-- SPEC LED 1 green : PLL status (DLD) |
-- SPEC LED 2 red : division of the 20 MHz clock |
-- |
-- There are also 4 LEDs and 2 buttons on the PCB of the SPEC carrier: |
......@@ -98,7 +98,7 @@ entity leds_manager is
internal_rst_i : in std_logic; -- core internal reset, synched with 125 MHz clk
-- Signal from the PLL
pll_ld_i : in std_logic; -- PLL lock detect
pll_status_i : in std_logic; -- PLL lock detect
-- Signals from the buttons on the SPEC PCB
spec_aux_butt_1_i : in std_logic; -- SPEC PCB button 1 (PB1)
......@@ -192,7 +192,7 @@ begin
---------------------------------------------------------------------------------------------------
-- SPEC FRONT PANEL LED 1 --
---------------------------------------------------------------------------------------------------
spec_led_green_o <= pll_ld_i;
spec_led_green_o <= pll_status_i;
---------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/tdc_core_pkg.vhd
View file @ 84739413
......@@ -487,14 +487,13 @@ package tdc_core_pkg is
(nb_of_reg : integer := 68);
port
(spec_clk_i : in std_logic;
acam_refclk_i : in std_logic;
acam_refclk_p_i : in std_logic;
acam_refclk_n_i : in std_logic;
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
rst_n_a_i : in std_logic;
pll_ld_i : in std_logic;
pll_refmon_i : in std_logic;
pll_sdo_i : in std_logic;
pll_status_i : in std_logic;
pll_sdo_i : in std_logic;
send_dac_word_p_i : in std_logic;
dac_word_i : in std_logic_vector(23 downto 0);
----------------------------------------------------------------------
......@@ -507,7 +506,7 @@ package tdc_core_pkg is
pll_dac_sync_o : out std_logic;
pll_sdi_o : out std_logic;
pll_sclk_o : out std_logic;
pll_ld_o : out std_logic);
pll_status_o : out std_logic);
----------------------------------------------------------------------
end component;
......@@ -522,7 +521,7 @@ package tdc_core_pkg is
clk_125mhz_i : in std_logic;
gnum_rst_i : in std_logic;
internal_rst_i : in std_logic;
pll_ld_i : in std_logic;
pll_status_i : in std_logic;
spec_aux_butt_1_i : in std_logic;
spec_aux_butt_2_i : in std_logic;
one_hz_p_i : in std_logic;
......@@ -549,8 +548,6 @@ package tdc_core_pkg is
port
(ef1_i : in std_logic;
ef2_i : in std_logic;
lf1_i : in std_logic; -- not used i think
lf2_i : in std_logic; -- not used i think
data_bus_io : inout std_logic_vector(27 downto 0);
clk_i : in std_logic;
rst_i : in std_logic;
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ 84739413
......@@ -17,7 +17,7 @@
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 06/2012 |
-- Version v2 |
-- Version v3 |
-- Depends on |
-- |
---------------- |
......@@ -32,7 +32,11 @@
-- interrupts generator added |
-- changed generation of general_rst |
-- DAC reconfiguration+needed regs added |
-- 06/2012 v3 EG Changes for v2 of TDC mezzanine |
-- Several pinout changes, |
-- acam_ref_clk LVDS instead of CMOS, |
-- no PLL_LD only PLL_STATUS |
-- |
----------------------------------------------/!\-------------------------------------------------|
-- TODO!! |
-- Data formatting unit, line 341: If a new tstamp has arrived from the ACAM when the roll_over |
......@@ -51,6 +55,13 @@
-- the new sec) that characterize the previous second!! |
-- Commented lines have not been tested at aaaaaall |
-- |
-- Interrupts generator unit, add interrupt "If N timestamps are available before a minimal time |
-- threshold occurs,no interrupt is raised and a flag is set indicating this condition"David's doc|
-- |
-- Clocks Resets Manager unit, check again PLL regs for acam_ref_clk (was CMOS in v1, now LVDS) |
-- |
-- Add logic for TDC_ERR?? |
-- Add logic for TDC_in_FPGA?? |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -66,18 +77,9 @@
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--
----------------------------------------------------------------------------------------------------
-- last changes:
-- revamping, comments, renamings etc
--
-- clks_rsts_mnger modified
----------------------------------------------------------------------------------------------------
-- to do:
----------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
......@@ -86,9 +88,9 @@ use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
----------------------------------------------------------------------------------------------------
-- entity declaration for top_tdc
----------------------------------------------------------------------------------------------------
--=================================================================================================
-- Entity declaration for top_tdc
--=================================================================================================
entity top_tdc is
generic
(g_span : integer :=32; -- address span in bus interfaces
......@@ -96,7 +98,7 @@ entity top_tdc is
values_for_simulation : boolean :=FALSE); -- this generic is set to TRUE
-- when instantiated in a test-bench
port
(-- interface with GNUM
(-- Signals for the GNUM interface
rst_n_a_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
......@@ -122,173 +124,134 @@ entity top_tdc is
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
spare_o : out std_logic;
-- interface signals with PLL circuit on TDC mezzanine
acam_refclk_i : in std_logic; -- 31.25 MHz clock that is also received by ACAM
pll_ld_i : in std_logic; -- PLL AD9516 interface signals
pll_refmon_i : in std_logic; --
pll_sdo_i : in std_logic; --
pll_status_i : in std_logic; --
-- Signal from the SPEC carrier
spec_clk_i : in std_logic ; -- 20 MHz clock from VCXO on SPEC
-- Signals for the SPI interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
pll_sclk_o : out std_logic; -- SPI clock
pll_sdi_o : out std_logic; -- data line for PLL and DAC
pll_cs_o : out std_logic; -- PLL chip select
pll_dac_sync_o : out std_logic; -- DAC chip select
pll_sdo_i : in std_logic; -- not used for the moment
pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
tdc_clk_p_i : in std_logic; -- 125 MHz differential clock : system clock
tdc_clk_n_i : in std_logic; --
pll_cs_o : out std_logic; -- PLL AD9516 interface signals
pll_dac_sync_o : out std_logic; --
pll_sdi_o : out std_logic; --
pll_sclk_o : out std_logic; --
-- interface signals with acam (timing) on TDC mezzanine
err_flag_i : in std_logic; -- error flag signal coming from ACAM
int_flag_i : in std_logic; -- interrupt flag signal coming from ACAM
start_dis_o : out std_logic; -- start disable signal for ACAM
start_from_fpga_o : out std_logic; -- start signal for ACAM
stop_dis_o : out std_logic; -- stop disable signal for ACAM
-- interface signals with acam (data) on TDC mezzanine
tdc_clk_n_i : in std_logic;
acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock, ACAM ref clock
acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock, ACAM ref clock
-- Signals for the timing interface with the ACAM on TDC mezzanine
err_flag_i : in std_logic; -- error flag
int_flag_i : in std_logic; -- interrupt flag
start_dis_o : out std_logic; -- start disable
start_from_fpga_o : out std_logic; -- start signal
stop_dis_o : out std_logic; -- stop disable
-- Signals for the data interface with the ACAM on TDC mezzanine
data_bus_io : inout std_logic_vector(27 downto 0);
ef1_i : in std_logic; -- empty flag iFIFO1 signal from ACAM
ef2_i : in std_logic; -- empty flag iFIFO2 signal from ACAM
lf1_i : in std_logic; -- load flag iFIFO1 signal from ACAM
lf2_i : in std_logic; -- load flag iFIFO2 signal from ACAM
address_o : out std_logic_vector(3 downto 0);
cs_n_o : out std_logic; -- chip select for ACAM
oe_n_o : out std_logic; -- output enable for ACAM
rd_n_o : out std_logic; -- read signal for ACAM
wr_n_o : out std_logic; -- write signal for ACAM
ef1_i : in std_logic; -- empty flag iFIFO1
ef2_i : in std_logic; -- empty flag iFIFO2
-- other signals on the TDC mezzanine
tdc_in_fpga_5_i : in std_logic; -- input 5 for ACAM is also received by FPGA
-- all 4 other stop inputs are miss-routed on PCB
mute_inputs_o : out std_logic; -- controls all 5 inputs (actual function: ENABLE)
tdc_led_status_o : out std_logic; -- amber led on front pannel
tdc_led_trig1_o : out std_logic; -- amber leds on front pannel
tdc_led_trig2_o : out std_logic; --
tdc_led_trig3_o : out std_logic; --
tdc_led_trig4_o : out std_logic; --
tdc_led_trig5_o : out std_logic; --
term_en_1_o : out std_logic; -- enable of 50 Ohm termination inputs
term_en_2_o : out std_logic; --
term_en_3_o : out std_logic; --
term_en_4_o : out std_logic; --
term_en_5_o : out std_logic; --
-- Carrier 1-wire interface (DS18B20 thermometer + unique ID)
--tdc_in_fpga_1_i : in std_logic; -- Ch.1 ACAM input also received by the FPGA, not used for the moment
--tdc_in_fpga_2_i : in std_logic; -- Ch.2 ACAM input also received by the FPGA, not used for the moment
--tdc_in_fpga_3_i : in std_logic; -- Ch.3 ACAM input also received by the FPGA, not used for the moment
--tdc_in_fpga_4_i : in std_logic; -- Ch.4 ACAM input also received by the FPGA, not used for the moment
--tdc_in_fpga_5_i : in std_logic; -- Ch.5 ACAM input also received by the FPGA, not used for the moment
-- Signals for the Input Logic on TDC mezzanine
enable_inputs_o : out std_logic; -- controls all 5 inputs
term_en_1_o : out std_logic; -- Ch.1 enable of 50 Ohm termination
term_en_2_o : out std_logic; -- Ch.2 enable of 50 Ohm termination
term_en_3_o : out std_logic; -- Ch.3 enable of 50 Ohm termination
term_en_4_o : out std_logic; -- Ch.4 enable of 50 Ohm termination
term_en_5_o : out std_logic; -- Ch.5 enable of 50 Ohm termination
-- LEDs on TDC mezzanine
tdc_led_status_o : out std_logic; -- amber led on front pannel,
tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-- Signal for the 1-wire interface (DS18B20 thermometer + unique ID) on SPEC carrier
carrier_one_wire_b : inout std_logic;
-- Mezzanine system I2C EEPROM
-- Signals for the I2C EEPROM interface on TDC mezzanine
sys_scl_b : inout std_logic; -- Mezzanine system I2C clock (EEPROM)
sys_sda_b : inout std_logic; -- Mezzanine system I2C data (EEPROM)
-- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
-- Signal for the 1-wire interface (DS18B20 thermometer + unique ID) on TDC mezzanine
mezz_one_wire_b : inout std_logic;
-- other signals on the SPEC carrier
-- Signals for the LEDs and Buttons on SPEC carrier
spec_led_green_o : out std_logic; -- green led on spec front pannel, PLL status
spec_led_red_o : out std_logic; -- red led on spec front pannel
spec_aux0_i : in std_logic; -- buttons on spec card
spec_aux1_i : in std_logic; --
spec_aux2_o : out std_logic; -- red leds on spec PCB
spec_aux3_o : out std_logic; --
spec_aux4_o : out std_logic; --
spec_aux5_o : out std_logic; --
spec_led_green_o : out std_logic; -- green led on spec front pannel
spec_led_red_o : out std_logic; -- red led on spec front pannel
spec_clk_i : in std_logic); -- 20 MHz clock from VCXO on spec card
spec_aux5_o : out std_logic); --
end top_tdc;
----------------------------------------------------------------------------------------------------
-- architecture declaration for top_tdc
----------------------------------------------------------------------------------------------------
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of top_tdc is
signal clk, spec_clk, pll_ld : std_logic;
-- LEDs
signal pulse_delay, window_delay, clk_period : std_logic_vector(g_width-1 downto 0);
signal gnum_rst : std_logic;
signal irq_code, core_status : std_logic_vector(g_width-1 downto 0);
signal acam_ef1, acam_ef2, acam_ef1_meta, acam_ef2_meta : std_logic;
signal acam_errflag_f_edge_p, acam_errflag_r_edge_p, acam_intflag_f_edge_p, acam_refclk_r_edge_p : std_logic;
signal acam_tstamp1, acam_tstamp2 : std_logic_vector(g_width-1 downto 0);
signal acam_tstamp1_ok_p, acam_tstamp2_ok_p : std_logic;
signal clk_i_cycles_offset, roll_over_nb, retrig_nb_offset : std_logic_vector(g_width-1 downto 0);
signal general_rst, general_rst_n : std_logic;
signal one_hz_p : std_logic;
signal acm_adr : std_logic_vector(7 downto 0);
-- clocks and resets
signal clk, spec_clk, pll_status : std_logic;
signal general_rst, general_rst_n, gnum_rst : std_logic;
-- TDC core signals
signal pulse_delay, window_delay, clk_period : std_logic_vector(g_width-1 downto 0);
signal irq_code, core_status : std_logic_vector(g_width-1 downto 0);
signal acam_ef1, acam_ef2, acam_ef1_meta, acam_ef2_meta : std_logic;
signal acam_errflag_f_edge_p, acam_errflag_r_edge_p : std_logic;
signal acam_intflag_f_edge_p, acam_refclk_r_edge_p : std_logic;
signal acam_tstamp1, acam_tstamp2 : std_logic_vector(g_width-1 downto 0);
signal acam_tstamp1_ok_p, acam_tstamp2_ok_p : std_logic;
signal clk_i_cycles_offset, roll_over_nb, retrig_nb_offset: std_logic_vector(g_width-1 downto 0);
signal one_hz_p : std_logic;
signal acm_adr : std_logic_vector(7 downto 0);
signal acm_cyc, acm_stb, acm_we, acm_ack : std_logic;
signal acm_dat_r, acm_dat_w : std_logic_vector(g_width-1 downto 0);
signal dma_irq : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
signal wbm_csr_sel : std_logic_vector(3 downto 0);
signal wbm_csr_stb, wbm_csr_we : std_logic;
signal acm_dat_r, acm_dat_w : std_logic_vector(g_width-1 downto 0);
signal activate_acq_p, deactivate_acq_p, load_acam_config : std_logic;
signal read_acam_config, read_acam_status, read_ififo1 : std_logic;
signal read_ififo2, read_start01, reset_acam, load_utc : std_logic;
signal clear_dacapo_counter, roll_over_incr_recent : std_logic;
signal starting_utc, acam_status, acam_inputs_en : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1, acam_ififo2, acam_start01 : std_logic_vector(g_width-1 downto 0);
signal irq_tstamp_threshold, irq_time_threshold : std_logic_vector(g_width-1 downto 0);
signal local_utc, wr_index : std_logic_vector(g_width-1 downto 0);
signal acam_config, acam_config_rdbk : config_vector;
signal tstamp_wr_p, irq_tstamp_p, irq_time_p, send_dac_word_p : std_logic;
signal pll_dac_word : std_logic_vector(23 downto 0);
-- GNUM core WISHBONE signals
signal wbm_csr_adr : std_logic_vector (31 downto 0);
signal wbm_csr_cyc, wbm_csr_ack_decoded, wbm_stall : std_logic;
signal wb_csr_cyc_decoded, wb_all_csr_ack, wb_all_csr_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_all_csr_dat_rd : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_csr_sel_decoded, wbm_csr_sel : std_logic_vector (3 downto 0);
signal wbm_csr_stb, wbm_csr_we : std_logic;
signal wbm_csr_dat_wr, wbm_csr_dat_rd, dma_dat_rd, dma_dat_wr : std_logic_vector(31 downto 0);
signal dma_stb, dma_cyc, dma_we, dma_ack, dma_stall : std_logic;
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal mem_class_adr : std_logic_vector(7 downto 0);
signal dma_stb, dma_cyc, dma_we, dma_ack, dma_stall : std_logic;
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal wb_csr_adr_decoded : std_logic_vector(g_span-1 downto 0);
signal wb_csr_dat_wr_decoded : std_logic_vector(g_width-1 downto 0);
signal wb_csr_stb_decoded, wb_csr_we_decoded : std_logic;
signal mem_class_adr : std_logic_vector(7 downto 0);
signal mem_class_stb, mem_class_cyc, mem_class_we, mem_class_ack : std_logic;
signal mem_class_data_wr, mem_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal wb_csr_adr_decoded : std_logic_vector(g_span-1 downto 0);
signal wb_csr_dat_wr_decoded : std_logic_vector(g_width-1 downto 0);
signal wb_csr_stb_decoded : std_logic;
signal wb_csr_we_decoded : std_logic;
signal activate_acq_p, deactivate_acq_p, load_acam_config, read_acam_config : std_logic;
signal read_acam_status, read_ififo1, read_ififo2, read_start01, reset_acam : std_logic;
signal load_utc, clear_dacapo_counter, roll_over_incr_recent : std_logic;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal acam_inputs_en, irq_tstamp_threshold, irq_time_threshold : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal acam_config_rdbk : config_vector;
signal acam_status, acam_ififo1, acam_ififo2, acam_start01 : std_logic_vector(g_width-1 downto 0);
signal local_utc, wr_index : std_logic_vector(g_width-1 downto 0);
signal irq_sources : std_logic_vector(g_width-1 downto 0);
signal wb_csr_cyc_decoded, wb_all_csr_ack, wb_all_csr_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_all_csr_dat_rd : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_csr_sel_decoded : std_logic_vector (3 downto 0);
signal wbm_csr_adr : std_logic_vector (31 downto 0);
signal wbm_csr_cyc, wbm_csr_ack_decoded, wbm_stall : std_logic;
signal mem_class_data_wr, mem_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
-- Interrupts
signal dma_irq : std_logic_vector(1 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources : std_logic_vector(g_width-1 downto 0);
-- Mezzanine 1-wire
signal mezz_owr_pwren : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal mezz_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal mezz_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal mezz_owr_pwren, mezz_owr_en, mezz_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-- Carrier 1-wire
signal carrier_owr_en : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal carrier_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONE_WIRE_NB - 1 downto 0);
-- Mezzanine system I2C for EEPROM
signal sys_scl_in, sys_scl_out, sys_scl_oe_n : std_logic;
signal sys_sda_in, sys_sda_out, sys_sda_oe_n : std_logic;
signal sys_scl_in, sys_scl_out, sys_scl_oe_n : std_logic;
signal sys_sda_in, sys_sda_out, sys_sda_oe_n : std_logic;
signal tstamp_wr_p, irq_tstamp_p, irq_time_p, send_dac_word_p : std_logic;
signal pll_dac_word : std_logic_vector(23 downto 0);
-- <acam_status_i<31:0>> is never used.
-- <adr_i<7:4>> is never used.
......@@ -302,12 +265,12 @@ architecture rtl of top_tdc is
-- <wbm_adr_i<31:18> never used
-- gnum_csr_adr_i<31:8> is never used
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
general_rst_n <= not (general_rst);
---------------------------------------------------------------------------------------------------
-- WISHBONE CSR DECODER --
---------------------------------------------------------------------------------------------------
......@@ -604,14 +567,14 @@ begin
begin
if rising_edge (clk) then
if general_rst = '1' then
mute_inputs_o <= '0';
enable_inputs_o <= '0';
term_en_5_o <= '0';
term_en_4_o <= '0';
term_en_3_o <= '0';
term_en_2_o <= '0';
term_en_1_o <= '0';
else
mute_inputs_o <= acam_inputs_en(7);
enable_inputs_o <= acam_inputs_en(7);
term_en_5_o <= acam_inputs_en(4);
term_en_4_o <= acam_inputs_en(3);
term_en_3_o <= acam_inputs_en(2);
......@@ -667,8 +630,6 @@ begin
port map
(ef1_i => ef1_i,
ef2_i => ef2_i,
lf1_i => lf1_i,
lf2_i => lf2_i,
data_bus_io => data_bus_io,
adr_o => address_o,
cs_n_o => cs_n_o,
......@@ -824,15 +785,14 @@ begin
---------------------------------------------------------------------------------------------------
clks_rsts_mgment: clks_rsts_manager
generic map
(nb_of_reg => 68)
(nb_of_reg => 68)
port map
(spec_clk_i => spec_clk_i,
acam_refclk_i => acam_refclk_i,
acam_refclk_p_i => acam_refclk_p_i,
acam_refclk_n_i => acam_refclk_n_i,
tdc_clk_p_i => tdc_clk_p_i,
tdc_clk_n_i => tdc_clk_n_i,
rst_n_a_i => rst_n_a_i,
pll_ld_i => pll_ld_i,
pll_refmon_i => pll_refmon_i,
pll_sdo_i => pll_sdo_i,
pll_status_i => pll_status_i,
send_dac_word_p_i => send_dac_word_p,
......@@ -846,7 +806,9 @@ begin
spec_clk_o => spec_clk,
tdc_clk_o => clk,
gnum_rst_o => gnum_rst,
pll_ld_o => pll_ld);
pll_status_o => pll_status);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
general_rst_n <= not (general_rst);
---------------------------------------------------------------------------------------------------
......@@ -861,7 +823,7 @@ begin
clk_125mhz_i => clk,
gnum_rst_i => gnum_rst,
internal_rst_i => general_rst,
pll_ld_i => pll_ld,
pll_status_i => pll_status,
spec_aux_butt_1_i => spec_aux0_i,
spec_aux_butt_2_i => spec_aux1_i,
one_hz_p_i => one_hz_p,
......
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