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FMC TDC 1ns 5cha - Gateware
Commit 8b1ee79a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fixes to accommodate interface changes by Eva

parent 2d2d830b
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Showing with 566 additions and 623 deletions
hdl/wr_spec_tdc/hdl/top/spec/fmc_tdc_wrapper.vhd
View file @ 8b1ee79a
......@@ -226,6 +226,17 @@ end fmc_tdc_wrapper;
--=================================================================================================
architecture rtl of fmc_tdc_wrapper is
component fmc_tdc_direct_readout is
port (
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
direct_timestamp_i : in std_logic_vector(127 downto 0);
direct_timestamp_wr_i : in std_logic;
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out);
end component fmc_tdc_direct_readout;
-----------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
......@@ -360,7 +371,6 @@ begin
wrabbit_time_valid_i => tm_time_valid_i,
wrabbit_cycles_i => tm_cycles_i,
wrabbit_utc_i => tm_tai_i(31 downto 0),
wrabbit_utc_p_o => open, -- for debug
wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en_o,
wrabbit_clk_aux_locked_i => tm_clk_aux_locked_i,
wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
......@@ -376,7 +386,7 @@ begin
i2c_scl_o => tdc_scl_out,
i2c_sda_o => tdc_sda_out,
-- 1-Wire on TDC mezzanine
one_wire_b => mezz_one_wire_b,
onewire_b => mezz_one_wire_b,
direct_timestamp_o => direct_timestamp,
direct_timestamp_stb_o => direct_timestamp_wr);
......
hdl/wr_spec_tdc/hdl/top/spec/tdc_core_pkg.vhd
View file @ 8b1ee79a
......@@ -52,9 +52,7 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wishbone_pkg.all;
use work.genram_pkg.all;
--use work.sdb_meta_pkg.all;
use work.gencores_pkg.all;
--=================================================================================================
......@@ -265,7 +263,7 @@ package tdc_core_pkg is
constant c_START_PHASE_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
constant c_ONE_HZ_PHASE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
constant c_IRQ_TSTAMP_THRESH_ADR : std_logic_vector(7 downto 0) := x"24"; -- address 0x51090 of GN4124 BAR 0
constant c_IRQ_TSTAMP_THRESH_ADR: std_logic_vector(7 downto 0) := x"24"; -- address 0x51090 of GN4124 BAR 0
constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 0x51094 of GN4124 BAR 0
constant c_DAC_WORD_ADR : std_logic_vector(7 downto 0) := x"26"; -- address 0x51098 of GN4124 BAR 0
......@@ -279,6 +277,9 @@ package tdc_core_pkg is
constant c_WR_INDEX_ADR : std_logic_vector(7 downto 0) := x"2A"; -- address 0x510A8 of GN4124 BAR 0
constant c_CORE_STATUS_ADR : std_logic_vector(7 downto 0) := x"2B"; -- address 0x510AC of GN4124 BAR 0
---------------------------------------------------------------------------------------------------
-- Addresses of the White Rabbit control and status registers
constant c_WRABBIT_STATUS_ADR : std_logic_vector(7 downto 0) := x"2C"; -- address 0x510B0 of GN4124 BAR 0
constant c_WRABBIT_CTRL_ADR : std_logic_vector(7 downto 0) := x"2D"; -- address 0x510B4 of GN4124 BAR 0
......@@ -322,7 +323,7 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
-- Constants regarding the One-Wire interface --
---------------------------------------------------------------------------------------------------
constant c_FMC_ONE_WIRE_NB : integer := 1;
constant c_FMC_ONEWIRE_NB : integer := 1;
---------------------------------------------------------------------------------------------------
......@@ -332,15 +333,18 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
-- Components Declarations: --
-- Components Declarations --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
component fmc_tdc_mezzanine is
generic
(g_span : integer := 32;
(g_with_wrabbit_core : boolean := TRUE;
g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := false);
values_for_simul : boolean := FALSE);
port
-- 62.5MHz clock and synchronous reset
(clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
-- Signals from the clks_rsts_manager unit
......@@ -385,14 +389,13 @@ package tdc_core_pkg is
wrabbit_time_valid_i : in std_logic;
wrabbit_cycles_i : in std_logic_vector(27 downto 0);
wrabbit_utc_i : in std_logic_vector(31 downto 0);
wrabbit_utc_p_o : out std_logic;
wrabbit_clk_aux_lock_en_o : out std_logic;
wrabbit_clk_aux_locked_i : in std_logic;
wrabbit_clk_dmtd_locked_i : in std_logic;
wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
wrabbit_dac_wr_p_i : in std_logic;
-- WISHBONE interface with the GN4124/VME_core
-- for the core configuration | core interrupts | 1Wire | I2C
-- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
wb_tdc_csr_adr_i : in std_logic_vector(31 downto 0);
wb_tdc_csr_dat_i : in std_logic_vector(31 downto 0);
wb_tdc_csr_cyc_i : in std_logic;
......@@ -403,10 +406,6 @@ package tdc_core_pkg is
wb_tdc_csr_ack_o : out std_logic;
wb_tdc_csr_stall_o : out std_logic;
wb_irq_o : out std_logic;
-- Interrupt pulses, for debug
irq_tstamp_p_o : out std_logic;
irq_time_p_o : out std_logic;
irq_acam_err_p_o : out std_logic;
-- I2C EEPROM interface
i2c_scl_o : out std_logic;
i2c_scl_oen_o : out std_logic;
......@@ -415,7 +414,7 @@ package tdc_core_pkg is
i2c_sda_oen_o : out std_logic;
i2c_sda_i : in std_logic;
-- 1-wire UniqueID&Thermometer interface
one_wire_b : inout std_logic;
onewire_b : inout std_logic;
direct_timestamp_o : out std_logic_vector(127 downto 0);
direct_timestamp_stb_o : out std_logic
);
......@@ -427,7 +426,7 @@ package tdc_core_pkg is
generic
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := false);
values_for_simul : boolean := FALSE);
port
(clk_125m_i : in std_logic;
rst_i : in std_logic;
......@@ -487,14 +486,12 @@ package tdc_core_pkg is
tdc_mem_wb_ack_o : out std_logic;
tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0);
tdc_mem_wb_stall_o : out std_logic;
direct_timestamp_o : out std_logic_vector(127 downto 0);
direct_timestamp_stb_o : out std_logic
);
);
end component;
---------------------------------------------------------------------------------------------------
component wrabbit_sync is
generic
......@@ -519,15 +516,6 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component spec_reset_gen is
port
(clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
---------------------------------------------------------------------------------------------------
component decr_counter
generic
......@@ -656,7 +644,6 @@ package tdc_core_pkg is
end component;
---------------------------------------------------------------------------------------------------
component reg_ctrl
generic
......@@ -718,7 +705,6 @@ package tdc_core_pkg is
clk_i : in std_logic;
activate_acq_p_i : in std_logic;
rst_i : in std_logic;
window_delay_i : in std_logic_vector(31 downto 0);
state_active_p_i : in std_logic;
deactivate_acq_p_i : in std_logic;
----------------------------------------------------------------------
......@@ -805,44 +791,6 @@ package tdc_core_pkg is
end component tdc_eic;
---------------------------------------------------------------------------------------------------
component dma_eic
port
(rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_dma_done_i : in std_logic;
irq_dma_error_i : in std_logic);
end component dma_eic;
---------------------------------------------------------------------------------------------------
component irq_controller
port
(clk_i : in std_logic;
rst_n_i : in std_logic;
irq_src_p_i : in std_logic_vector(31 downto 0);
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
----------------------------------------------------------------------
wb_dat_o : out std_logic_vector(31 downto 0);
wb_ack_o : out std_logic;
irq_p_o : out std_logic);
end component irq_controller;
---------------------------------------------------------------------------------------------------
component clks_rsts_manager
generic
......@@ -910,7 +858,7 @@ package tdc_core_pkg is
component leds_manager is
generic
(g_width : integer := 32;
values_for_simul : boolean := false);
values_for_simul : boolean := FALSE);
port
(clk_i : in std_logic;
rst_i : in std_logic;
......@@ -1050,11 +998,9 @@ package tdc_core_pkg is
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
mezz_one_wire_b : inout std_logic;
mezz_scl_b : inout std_logic;
mezz_sda_b : inout std_logic;
mezz_one_wire_b : inout std_logic;
tm_link_up_i : in std_logic;
tm_time_valid_i : in std_logic;
tm_cycles_i : in std_logic_vector(27 downto 0);
......@@ -1066,25 +1012,12 @@ package tdc_core_pkg is
tm_dac_wr_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out;
irq_o : out std_logic;
clk_125m_tdc_o: out std_logic);
clk_125m_tdc_o : out std_logic);
end component fmc_tdc_wrapper;
component fmc_tdc_direct_readout is
port (
clk_tdc_i : in std_logic;
rst_tdc_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
direct_timestamp_i : in std_logic_vector(127 downto 0);
direct_timestamp_wr_i : in std_logic;
direct_slave_i : in t_wishbone_slave_in;
direct_slave_o : out t_wishbone_slave_out);
end component fmc_tdc_direct_readout;
end tdc_core_pkg;
--=================================================================================================
......@@ -1092,7 +1025,6 @@ end tdc_core_pkg;
--=================================================================================================
package body tdc_core_pkg is
end tdc_core_pkg;
--=================================================================================================
-- package end
......@@ -1100,3 +1032,4 @@ end tdc_core_pkg;
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
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