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FMC TDC 1ns 5cha - Gateware
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FMC TDC 1ns 5cha - Gateware
Commits
9f4f8fd2
Commit
9f4f8fd2
authored
Nov 24, 2017
by
Tomasz Wlostowski
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Plain Diff
fmc_tdc_core: decrease timestamp FIFO size to 512 (so that it fits in the SPEC with WPRC v4.1)
parent
3b60a1ec
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5 changed files
with
187 additions
and
190 deletions
+187
-190
fmc_tdc_core.vhd
hdl/rtl/fmc_tdc_core.vhd
+176
-170
timestamp_fifo.vhd
hdl/rtl/timestamp_fifo.vhd
+1
-1
timestamp_fifo_wb.vhd
hdl/rtl/timestamp_fifo_wb.vhd
+7
-16
timestamp_fifo_wbgen2_pkg.vhd
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
+2
-2
timestamp_fifo_wb.wb
hdl/rtl/wbgen/timestamp_fifo_wb.wb
+1
-1
No files found.
hdl/rtl/fmc_tdc_core.vhd
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9f4f8fd2
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hdl/rtl/timestamp_fifo.vhd
View file @
9f4f8fd2
...
...
@@ -113,7 +113,7 @@ begin
regs_i
=>
regs_in
,
regs_o
=>
regs_out
);
buf_count
<=
unsigned
(
regs_out
.
fifo_wr_usedw_o
);
buf_count
<=
resize
(
unsigned
(
regs_out
.
fifo_wr_usedw_o
),
10
);
ts_match
<=
'1'
when
timestamp_valid_i
=
'1'
and
unsigned
(
timestamp_i
(
98
downto
96
))
=
g_channel
else
'0'
;
...
...
hdl/rtl/timestamp_fifo_wb.vhd
View file @
9f4f8fd2
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wb.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created :
Mon Apr 20 17:34:12 2015
-- Created :
Wed Sep 20 18:41:08 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
...
...
@@ -89,26 +89,16 @@ signal tsf_csr_rst_seq_sync2 : std_logic ;
signal
tsf_fifo_full_int
:
std_logic
;
signal
tsf_fifo_empty_int
:
std_logic
;
signal
tsf_fifo_clear_bus_int
:
std_logic
;
signal
tsf_fifo_usedw_int
:
std_logic_vector
(
9
downto
0
);
signal
tsf_fifo_usedw_int
:
std_logic_vector
(
8
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
3
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments
. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
...
...
@@ -310,7 +300,8 @@ begin
rddata_reg
(
16
)
<=
tsf_fifo_full_int
;
rddata_reg
(
17
)
<=
tsf_fifo_empty_int
;
rddata_reg
(
18
)
<=
'0'
;
rddata_reg
(
9
downto
0
)
<=
tsf_fifo_usedw_int
;
rddata_reg
(
8
downto
0
)
<=
tsf_fifo_usedw_int
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
...
...
@@ -353,9 +344,9 @@ begin
tsf_fifo_rst_n
<=
rst_n_i
and
(
not
tsf_fifo_clear_bus_int
);
tsf_fifo_INST
:
wbgen2_fifo_async
generic
map
(
g_size
=>
1024
,
g_size
=>
512
,
g_width
=>
128
,
g_usedw_size
=>
10
g_usedw_size
=>
9
)
port
map
(
wr_req_i
=>
regs_i
.
fifo_wr_req_i
,
...
...
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
View file @
9f4f8fd2
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created :
Mon Apr 20 17:34:12 2015
-- Created :
Wed Sep 20 18:41:08 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
...
...
@@ -51,7 +51,7 @@ package tsf_wbgen2_pkg is
type
t_tsf_out_registers
is
record
fifo_wr_full_o
:
std_logic
;
fifo_wr_empty_o
:
std_logic
;
fifo_wr_usedw_o
:
std_logic_vector
(
9
downto
0
);
fifo_wr_usedw_o
:
std_logic_vector
(
8
downto
0
);
csr_last_valid_o
:
std_logic
;
csr_last_valid_load_o
:
std_logic
;
csr_rst_seq_o
:
std_logic
;
...
...
hdl/rtl/wbgen/timestamp_fifo_wb.wb
View file @
9f4f8fd2
...
...
@@ -9,7 +9,7 @@ peripheral {
-- TXTSU shared FIFO
fifo_reg {
size =
1024
; -- or more. We'll see :)
size =
512
; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "fifo";
name = "Timestamp FIFO";
...
...
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