Commit a03c43a2 authored by penacoba's avatar penacoba

trying to cleanup svn


git-svn-id: http://svn.ohwr.org/fmc-tdc@73 85dfdc96-de2c-444c-878d-45b388be74a9
parent 17667554
750 us,5,505 ns
1850 us,1,5 us
2600 us,1,5 us
800 us,2,505 ns
162 ps,3,505 ns
500 us,4,505 ns
400 ps,1,505 ns
18 ps,5,505 ns
600 ns,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
110 ps,1,100 ps
110 ps,2,100 ps
110 ps,3,100 ps
probe -create -shm -waveform :dut:acam_refclk
probe -create -shm -waveform :dut:acam_refclk_i
probe -create -shm -waveform :spec_clk_i
probe -create -shm -waveform :dut:clk
probe -create -shm -waveform :dut:gnum_reset
......@@ -23,64 +23,6 @@ probe -create -shm -waveform :dut:general_reset
#probe -create -shm -waveform :dut:tdc_led_count_done
#probe -create -shm -waveform :dut:spec_led_count_done
#probe -create -shm -waveform :dut:one_second_block:refclk_edge
#probe -create -shm -waveform :dut:one_second_block:onesec_counter_en
#probe -create -shm -waveform :dut:one_second_block:clock_periods_counter:current_value
#probe -create -shm -waveform :dut:one_second_block:total_delay
#probe -create -shm -waveform :dut:one_second_block:pulse_delayer_counter:current_value
#probe -create -shm -waveform :dut:one_second_block:one_hz_p_pre
#probe -create -shm -waveform :dut:one_second_block:one_hz_p_post
probe -create -shm -waveform :dut:one_second_block:one_hz_p_o
probe -create -shm -waveform :dut:int_flag_i
probe -create -shm -waveform :dut:acam_fall_intflag_p
#probe -create -shm -waveform :dut:start_retrigger_block:roll_over_reset
#probe -create -shm -waveform :dut:start_retrigger_block:add_roll_over
probe -create -shm -waveform :dut:start_retrigger_block:roll_over_value
#probe -create -shm -waveform :dut:start_retrigger_block:retrig_nb_reset
probe -create -shm -waveform :dut:start_retrigger_block:current_retrig_nb
#probe -create -shm -waveform :dut:start_retrigger_block:retrig_period_reset
probe -create -shm -waveform :dut:start_retrigger_block:retrig_p
probe -create -shm -waveform :dut:start_retrigger_block:current_cycles
probe -create -shm -waveform :dut:start_retrigger_block:clk_cycles_offset
probe -create -shm -waveform :dut:start_retrigger_block:retrig_nb_offset
probe -create -shm -waveform :dut:start_trig
probe -create -shm -waveform :dut:acam_timing_block:start_trig_edge
probe -create -shm -waveform :dut:acam_timing_block:window_delay
#probe -create -shm -waveform :dut:acam_timing_block:waitingfor_refclk
probe -create -shm -waveform :dut:acam_timing_block:refclk_edge
probe -create -shm -waveform :dut:acam_timing_block:window_prepulse
#probe -create -shm -waveform :dut:acam_timing_block:start_trig_received
#probe -create -shm -waveform :dut:acam_timing_block:counter_reset
#probe -create -shm -waveform :dut:acam_timing_block:window_active
#probe -create -shm -waveform :dut:acam_timing_block:counter_value
#probe -create -shm -waveform :start_dis_o
probe -create -shm -waveform :start_from_fpga_o
#probe -create -shm -waveform :stop_dis_o
#probe -create -shm -waveform :acam:timing_block:start01
#probe -create -shm -waveform :acam:timing_block:start_retrig_p
#probe -create -shm -waveform :acam:timing_block:start_retrig_nb
#probe -create -shm -waveform :dut:acam_timing_block:int_flag_i
#probe -create -shm -waveform :dut:start_retrigger_block:acam_fall_intflag_p_i
#probe -create -shm -waveform :dut:start_retrigger_block:acam_rise_intflag_p_i
#probe -create -shm -waveform :dut:start_retrigger_block:acam_halfcounter_gone
#probe -create -shm -waveform :dut:start_retrigger_block:add_offset
#probe -create -shm -waveform :dut:start_retrigger_block:start_nb_offset_o
probe -create -shm -waveform :tstop1
probe -create -shm -waveform :tstop2
probe -create -shm -waveform :tstop3
probe -create -shm -waveform :tstop4
probe -create -shm -waveform :tstop5
probe -create -shm -waveform :dut:data_formatting_block:local_utc
probe -create -shm -waveform :dut:data_formatting_block:coarse_time
probe -create -shm -waveform :dut:data_formatting_block:fine_time
#probe -create -shm -waveform :RSTINn
#probe -create -shm -waveform :RSTOUT18n
#probe -create -shm -waveform :RSTOUT33n
......@@ -133,6 +75,7 @@ probe -create -shm -waveform :dut:load_acam_config
probe -create -shm -waveform :dut:read_acam_config
probe -create -shm -waveform :dut:read_acam_status
probe -create -shm -waveform :dut:reset_acam
probe -create -shm -waveform :dut:clk
probe -create -shm -waveform :dut:data_engine_block:engine_st
probe -create -shm -waveform :dut:acm_adr
......@@ -146,7 +89,9 @@ probe -create -shm -waveform :dut:acm_dat_r
#probe -create -shm -waveform :dut:acam_data_block:nxt_acam_data_st
probe -create -shm -waveform :dut:ef1_i
probe -create -shm -waveform :dut:acam_data_block:ef1_r
probe -create -shm -waveform :dut:ef2_i
probe -create -shm -waveform :dut:acam_data_block:ef2_r
probe -create -shm -waveform :dut:lf1_i
probe -create -shm -waveform :dut:lf2_i
probe -create -shm -waveform :dut:data_bus_io
......@@ -155,12 +100,68 @@ probe -create -shm -waveform :dut:cs_n_o
probe -create -shm -waveform :dut:oe_n_o
probe -create -shm -waveform :dut:rd_n_o
probe -create -shm -waveform :dut:wr_n_o
waveform format -using "Waveform 1" ":dut:rd_n_o" -color "red"
probe -create -shm -waveform :dut:acam_data_block:acam_data_st
#probe -create -shm -waveform :dut:acam_data_block:wr_extend
#probe -create -shm -waveform :dut:acam_data_block:wr_remove
#probe -create -shm -waveform :dut:acam_data_block:wr
waveform format -using "Waveform 1" ":dut:wr_n_o" -color "magenta"
#probe -create -shm -waveform :dut:clks_rsts_mgment:acam_refclk_i
#probe -create -shm -waveform :dut:clks_rsts_mgment:acam_refclk_r
#probe -create -shm -waveform :dut:clks_rsts_mgment:acam_refclk_edge_p
#probe -create -shm -waveform :dut:one_second_block:acam_refclk_edge_p
#probe -create -shm -waveform :dut:one_second_block:onesec_counter_en
#probe -create -shm -waveform :dut:one_second_block:clock_periods_counter:current_value
#probe -create -shm -waveform :dut:one_second_block:total_delay
#probe -create -shm -waveform :dut:one_second_block:pulse_delayer_counter:current_value
#probe -create -shm -waveform :dut:one_second_block:one_hz_p_pre
#probe -create -shm -waveform :dut:one_second_block:one_hz_p_post
probe -create -shm -waveform :dut:one_second_block:one_hz_p_o
probe -create -shm -waveform :dut:int_flag_i
probe -create -shm -waveform :dut:acam_fall_intflag_p
#probe -create -shm -waveform :dut:start_retrigger_block:roll_over_reset
#probe -create -shm -waveform :dut:start_retrigger_block:add_roll_over
probe -create -shm -waveform :dut:start_retrigger_block:roll_over_value
#probe -create -shm -waveform :dut:start_retrigger_block:retrig_nb_reset
probe -create -shm -waveform :dut:start_retrigger_block:current_retrig_nb
#probe -create -shm -waveform :dut:start_retrigger_block:retrig_period_reset
probe -create -shm -waveform :dut:start_retrigger_block:retrig_p
probe -create -shm -waveform :dut:start_retrigger_block:current_cycles
probe -create -shm -waveform :dut:start_retrigger_block:clk_cycles_offset
probe -create -shm -waveform :dut:start_retrigger_block:retrig_nb_offset
probe -create -shm -waveform :dut:acam_timing_block:start_trig
probe -create -shm -waveform :dut:acam_timing_block:start_trig_r
probe -create -shm -waveform :dut:acam_timing_block:start_trig_edge
probe -create -shm -waveform :dut:acam_timing_block:window_delay
#probe -create -shm -waveform :dut:acam_timing_block:waitingfor_refclk
probe -create -shm -waveform :dut:acam_timing_block:refclk_edge
probe -create -shm -waveform :dut:acam_timing_block:window_prepulse
#probe -create -shm -waveform :dut:acam_timing_block:start_trig_received
#probe -create -shm -waveform :dut:acam_timing_block:counter_reset
#probe -create -shm -waveform :dut:acam_timing_block:window_active
#probe -create -shm -waveform :dut:acam_timing_block:counter_value
#probe -create -shm -waveform :start_dis_o
probe -create -shm -waveform :start_from_fpga_o
#probe -create -shm -waveform :stop_dis_o
#probe -create -shm -waveform :acam:timing_block:start01
#probe -create -shm -waveform :acam:timing_block:start_retrig_p
#probe -create -shm -waveform :acam:timing_block:start_retrig_nb
#probe -create -shm -waveform :dut:acam_timing_block:int_flag_i
#probe -create -shm -waveform :dut:start_retrigger_block:acam_fall_intflag_p_i
#probe -create -shm -waveform :dut:start_retrigger_block:acam_rise_intflag_p_i
#probe -create -shm -waveform :dut:start_retrigger_block:acam_halfcounter_gone
#probe -create -shm -waveform :dut:start_retrigger_block:add_offset
#probe -create -shm -waveform :dut:start_retrigger_block:start_nb_offset_o
probe -create -shm -waveform :tstop1
probe -create -shm -waveform :tstop2
probe -create -shm -waveform :tstop3
probe -create -shm -waveform :tstop4
probe -create -shm -waveform :tstop5
probe -create -shm -waveform :dut:acam_timestamp1
probe -create -shm -waveform :dut:acam_timestamp1_valid
......@@ -173,7 +174,8 @@ probe -create -shm -waveform :dut:data_formatting_block:coarse_time
probe -create -shm -waveform :dut:data_formatting_block:fine_time
probe -create -shm -waveform :dut:data_formatting_block:wr_pointer
probe -create -shm -waveform :dut:wr_pointer
probe -create -shm -waveform :dut:data_formatting_block:dacapo_counter
probe -create -shm -waveform :dut:wr_index
probe -create -shm -waveform :dut:mem_class_adr
probe -create -shm -waveform :dut:mem_class_cyc
......
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Bitgen" num="341" delta="new" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, requires a special bit stream format. For more information, please reference Xilinx Answer Record 39999.
</msg>
<msg type="warning" file="PhysDesignRules" num="2410" delta="new" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
</msg>
</messages>
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="NgdBuild" num="931" delta="new" >The value of SIM_DEVICE on instance &apos;<arg fmt="%s" index="1">gnum_interface_block.cmp_clk_in.rx_pll_adv_inst</arg>&apos; of type <arg fmt="%s" index="2">PLL_ADV</arg> has been changed from &apos;<arg fmt="%s" index="3">VIRTEX5</arg>&apos; to &apos;<arg fmt="%s" index="4">SPARTAN6</arg>&apos; to correct post-ngdbuild and timing simulation for this primitive. In order for functional simulation to be correct, the value of SIM_DEVICE should be changed in this same manner in the source netlist or constraint file.
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="new" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">gnum_interface_block_cmp_clk_in_buf_P_clk</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_gnum_interface_block_cmp_clk_in_buf_P_clk</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">gnum_interface_block.cmp_clk_in.rx_pll_adv_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT0</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_gnum_interface_block_un1_cmp_clk_in = PERIOD &quot;gnum_interface_block_un1_cmp_clk_in&quot; TS_gnum_interface_block_cmp_clk_in_buf_P_clk / 2 HIGH 50%&gt;</arg>
</msg>
<msg type="info" file="ConstraintSystem" num="178" delta="new" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">gnum_interface_block_cmp_clk_in_buf_P_clk</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_gnum_interface_block_cmp_clk_in_buf_P_clk</arg>&apos;, was traced into <arg fmt="%s" index="4">PLL_ADV</arg> instance <arg fmt="%s" index="5">gnum_interface_block.cmp_clk_in.rx_pll_adv_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">PLL_ADV</arg> output(s):
<arg fmt="%s" index="7">CLKOUT2</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_gnum_interface_block_cmp_clk_in_rx_pllout_x1_0 = PERIOD &quot;gnum_interface_block_cmp_clk_in_rx_pllout_x1_0&quot; TS_gnum_interface_block_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%&gt;</arg>
</msg>
<msg type="warning" file="ConstraintSystem" num="0" >The Offset constraint &lt;TIMEGRP &quot;acam_refclk_i&quot; OFFSET = IN: 6.000 : BEFORE tdc_clk_p_i;&gt; [synplicity.ucf(49)], is specified without a duration. This will result in a lack of hold time checks in timing reports. If hold time checks are desired a duration value should be specified following the &apos;VALID&apos; keyword.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="0" >The Offset constraint &lt;TIMEGRP &quot;acam_refclk_i&quot; OFFSET = IN 6 ns BEFORE COMP &quot;tdc_clk_p_i&quot;;&gt; [syn_tdc.pcf(11480)], is specified without a duration. This will result in a lack of hold time checks in timing reports. If hold time checks are desired a duration value should be specified following the &apos;VALID&apos; keyword.
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_1035_1 = MAXDELAY FROM TIMEGRP &quot;from_1035_1&quot; TO TIMEGRP &quot;to_1035_0&quot; 20 ns;</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">tdc_in_fpga_5_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">vc_rdy_i(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">vc_rdy_i(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p_wr_req_i(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p_wr_req_i(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">tx_error_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">pll_sdo_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">pll_refmon_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">err_flag_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">pll_status_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="468" delta="new" >Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select &quot;Post-Place &amp;
Route Static Timing Report&quot;). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -&gt; Design Goals &amp; Strategies) to ensure the best options are set in the tools for timing closure.
</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">10</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">10</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="ConstraintSystem" num="0" >The Offset constraint &lt;TIMEGRP &quot;acam_refclk_i&quot; OFFSET = IN 6 ns BEFORE COMP &quot;tdc_clk_p_i&quot;;&gt; [syn_tdc.pcf(11480)], is specified without a duration. This will result in a lack of hold time checks in timing reports. If hold time checks are desired a duration value should be specified following the &apos;VALID&apos; keyword.
</msg>
<msg type="warning" file="Timing" num="3223" delta="new" >Timing constraint <arg fmt="%s" index="1">TS_1035_1 = MAXDELAY FROM TIMEGRP &quot;from_1035_1&quot; TO TIMEGRP &quot;to_1035_0&quot; 20 ns;</arg> ignored during timing analysis.</msg>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
</messages>
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rm -r backup
rm -r coreip
rm identify.log
rm rpt_top_tdc.areasrr rpt_top_tdc_areasrr.htm
rm run_ise.tcl
rm run_options.txt scratchproject.prs
rm synplicity.ucf
rm fifo_32x512.ngc
rm fifo_64x512.ngc
rm syn_tdc.edf
rm syn_tdc.fse
rm syn_tdc.htm
rm syn_tdc.map
rm syn_tdc.ncf
rm syn_tdc_prepass.srd
rm syn_tdc.sap
rm syn_tdc.srd
rm syn_tdc.srl
rm syn_tdc.srm
rm syn_tdc.srr
rm syn_tdc.srs
rm syn_tdc.szr
rm syn_tdc.tlg
rm -r syntmp
rm -r xplace
rm syn_tdc.bld
rm syn_tdc.mrp
rm syn_tdc.ncd
rm syn_tdc.ngd
rm syn_tdc_ngdbuild.xrpt
rm syn_tdc.ngm
rm syn_tdc.ngo
rm syn_tdc.pcf
rm syn_tdc_summary.xml
rm syn_tdc_usage.xml
rm top_tdc_map.xrpt
rm top_tdc_par.xrpt
rm -r xlnx_auto_0_xdb
rm -r _xmsgs
rm netlist.lst
rm par_tdc.ncd
rm par_tdc.pad
rm par_tdc_pad.csv
rm par_tdc_pad.txt
rm par_tdc.par
rm par_tdc.ptwx
rm par_tdc.unroutes
rm par_tdc.xpi
rm par_usage_statistics.html
rm timing_report.twr
rm timing_report.twx
rm tdc.bgn
rm tdc.bit
rm tdc_bitgen.xwbt
rm tdc.drc
rm webtalk.log
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/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/syn_tdc.edf 1320402962
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/blk_mem_circ_buff_v6_4.ngc 1320402903
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_64x512.ngc 1320402903
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_32x512.ngc 1320402903
OK
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