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FMC TDC 1ns 5cha - Gateware
Commit b5ae1362 authored by penacoba's avatar penacoba
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Improved version of PLL test + first operating version of ACAM test 


git-svn-id: http://svn.ohwr.org/fmc-tdc@34 85dfdc96-de2c-444c-878d-45b388be74a9
parent c86fe33b
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Showing with 132 additions and 65 deletions
hdl/spec/src/ip_cores/gnum_core/gn4124_core_s6.vhd
View file @ b5ae1362
...@@ -340,6 +340,17 @@ begin ...@@ -340,6 +340,17 @@ begin
PLLD => 1, PLLD => 1,
PLLX => 2, PLLX => 2,
S => 2, S => 2,
-- CLKIN_PERIOD => 10.000,
-- PLLD => 2,
-- PLLX => 8,
-- S => 4,
-- CLKIN_PERIOD => 6.25,
-- PLLD => 1,
-- PLLX => 2,
-- S => 2,
BS => false) BS => false)
port map ( port map (
clkin_p => p2l_clk_p_i, clkin_p => p2l_clk_p_i,
......
hdl/spec/src/rtl/acam_databus_interface.vhd
View file @ b5ae1362
...@@ -184,7 +184,7 @@ begin ...@@ -184,7 +184,7 @@ begin
adr <= adr_i; adr <= adr_i;
cyc <= cyc_i; cyc <= cyc_i;
data_bus_io <= dat_i(27 downto 0); data_bus_io <= dat_i(27 downto 0) when we='1' else (others =>'Z');
stb <= stb_i; stb <= stb_i;
we <= we_i; we <= we_i;
......
hdl/spec/src/rtl/clk_rst_managr.vhd
View file @ b5ae1362
...@@ -31,7 +31,8 @@ use UNISIM.vcomponents.all; ...@@ -31,7 +31,8 @@ use UNISIM.vcomponents.all;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
entity clk_rst_managr is entity clk_rst_managr is
generic( generic(
nb_of_reg : integer:=68 nb_of_reg : integer:=68;
values_for_simulation : boolean:=FALSE
); );
port( port(
acam_refclk_i : in std_logic; acam_refclk_i : in std_logic;
...@@ -164,31 +165,36 @@ constant reg_230 : t_byte:=x"00"; ...@@ -164,31 +165,36 @@ constant reg_230 : t_byte:=x"00";
constant reg_231 : t_byte:=x"00"; constant reg_231 : t_byte:=x"00";
constant reg_232 : t_byte:=x"01"; constant reg_232 : t_byte:=x"01";
signal pll_init_st : t_pll_init_st; constant sim_reset : std_logic_vector(31 downto 0):=x"00000400";
signal nxt_pll_init_st : t_pll_init_st; constant syn_reset : std_logic_vector(31 downto 0):=x"00004E20";
signal config_reg : t_stream;
signal address : t_instr;
signal acam_refclk_buf : std_logic; signal pll_init_st : t_pll_init_st;
signal spec_clk_buf : std_logic; signal nxt_pll_init_st : t_pll_init_st;
signal tdc_clk_buf : std_logic;
signal acam_refclk : std_logic; signal config_reg : t_stream;
signal pll_sclk : std_logic; signal address : t_instr;
signal spec_clk : std_logic;
signal tdc_clk : std_logic;
signal bit_being_sent : std_logic; signal acam_refclk_buf : std_logic;
signal word_being_sent : t_wd; signal spec_clk_buf : std_logic;
signal bit_index : integer range 15 downto 0; signal tdc_clk_buf : std_logic;
signal byte_index : integer range nb_of_reg-1 downto 0;
signal acam_refclk : std_logic;
signal silly_altern : std_logic; signal pll_sclk : std_logic;
signal gnum_reset : std_logic; signal spec_clk : std_logic;
signal gral_incr : std_logic; signal tdc_clk : std_logic;
signal inv_reset : std_logic;
signal cs : std_logic; signal bit_being_sent : std_logic;
signal word_being_sent : t_wd;
signal bit_index : integer range 15 downto 0;
signal byte_index : integer range nb_of_reg-1 downto 0;
signal silly_altern : std_logic;
signal gnum_reset : std_logic;
signal gral_incr : std_logic;
signal gral_reset_duration : std_logic_vector(31 downto 0);
signal inv_reset : std_logic;
signal cs : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
...@@ -243,7 +249,7 @@ begin ...@@ -243,7 +249,7 @@ begin
general_poreset: incr_counter general_poreset: incr_counter
port map( port map(
clk => spec_clk, clk => spec_clk,
end_value => x"0000007D", -- 125 clk ticks end_value => gral_reset_duration,
incr => gral_incr, incr => gral_incr,
reset => gnum_reset, reset => gnum_reset,
...@@ -251,6 +257,9 @@ begin ...@@ -251,6 +257,9 @@ begin
current_value => open current_value => open
); );
gral_reset_duration <= sim_reset when values_for_simulation
else syn_reset;
silly: process silly: process
begin begin
if gnum_reset ='1' then if gnum_reset ='1' then
......
hdl/spec/src/rtl/tdc_core_pkg.vhd
View file @ b5ae1362
...@@ -71,11 +71,12 @@ package tdc_core_pkg is ...@@ -71,11 +71,12 @@ package tdc_core_pkg is
); );
end component; end component;
constant data_width : integer:=32; constant data_width : integer:=32;
constant tdc_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"0000F424"; constant tdc_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"0000F424"; -- 500 us at 125 MHz
constant tdc_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"03B9ACA0"; constant tdc_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"03B9ACA0"; -- 500 ms at 125 MHz
constant spec_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"00004E20"; constant spec_led_period_sim : std_logic_vector(data_width-1 downto 0):=x"00004E20"; -- 1 ms at 20 MHz
constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"01312D00"; constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"01312D00"; -- 1 s at 20 MHz
constant visible_blink_length : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; constant blink_length_syn : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; -- 100 ms at 125 MHz
constant blink_length_sim : std_logic_vector(data_width-1 downto 0):=x"000004E2"; -- 10 us at 125 MHz
end tdc_core_pkg; end tdc_core_pkg;
......
hdl/spec/src/rtl/test_tdc_acam/top_test_acam.vhd
View file @ b5ae1362
...@@ -225,6 +225,10 @@ architecture rtl of top_tdc is ...@@ -225,6 +225,10 @@ architecture rtl of top_tdc is
end component; end component;
component clk_rst_managr component clk_rst_managr
generic(
nb_of_reg : integer:=68;
values_for_simulation : boolean:=FALSE
);
port( port(
acam_refclk_i : in std_logic; acam_refclk_i : in std_logic;
pll_ld_i : in std_logic; pll_ld_i : in std_logic;
...@@ -335,11 +339,10 @@ architecture rtl of top_tdc is ...@@ -335,11 +339,10 @@ architecture rtl of top_tdc is
--used to generate the one_hz_p pulse --used to generate the one_hz_p pulse
constant sim_clock_period : std_logic_vector(g_width-1 downto 0):=x"0001E848"; -- 1 ms at 125 MHz (tdc board clock) constant sim_clock_period : std_logic_vector(g_width-1 downto 0):=x"0001E848"; -- 1 ms at 125 MHz (tdc board clock)
constant syn_clock_period : std_logic_vector(g_width-1 downto 0):=x"07735940"; -- 1 s at 125 MHz (tdc board clock) constant syn_clock_period : std_logic_vector(g_width-1 downto 0):=x"07735940"; -- 1 s at 125 MHz (tdc board clock)
-- used for regular blinking of the red led
constant spec_led_period_sim : std_logic_vector(g_width-1 downto 0):=x"00004E20"; -- 1 ms at 20 MHz (spec board clock)
constant spec_led_period_syn : std_logic_vector(g_width-1 downto 0):=x"01312D00"; -- 1 s at 20 MHz (spec board clock)
signal spec_led_period : std_logic_vector(g_width-1 downto 0); signal spec_led_period : std_logic_vector(g_width-1 downto 0);
signal tdc_led_period : std_logic_vector(g_width-1 downto 0);
signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
signal tdc_led_count_done : std_logic; signal tdc_led_count_done : std_logic;
signal spec_led_count_done : std_logic; signal spec_led_count_done : std_logic;
...@@ -568,6 +571,10 @@ begin ...@@ -568,6 +571,10 @@ begin
); );
clks_rsts_mgment: clk_rst_managr clks_rsts_mgment: clk_rst_managr
generic map(
nb_of_reg => 68,
values_for_simulation => values_for_simulation
)
port map( port map(
acam_refclk_i => acam_refclk_i, acam_refclk_i => acam_refclk_i,
pll_ld_i => pll_ld_i, pll_ld_i => pll_ld_i,
...@@ -581,7 +588,7 @@ begin ...@@ -581,7 +588,7 @@ begin
acam_refclk_o => acam_refclk, acam_refclk_o => acam_refclk,
general_reset_o => general_reset, general_reset_o => general_reset,
pll_cs_o => pll_cs, pll_cs_o => pll_cs_o,
pll_dac_sync_o => pll_dac_sync_o, pll_dac_sync_o => pll_dac_sync_o,
pll_sdi_o => pll_sdi_o, pll_sdi_o => pll_sdi_o,
pll_sclk_o => pll_sclk_o, pll_sclk_o => pll_sclk_o,
...@@ -589,6 +596,35 @@ begin ...@@ -589,6 +596,35 @@ begin
tdc_clk_o => clk tdc_clk_o => clk
); );
tdc_led_counter: countdown_counter
port map(
clk => clk,
reset => general_reset,
start => one_hz_p,
start_value => visible_blink_length,
count_done => tdc_led_count_done,
current_value => open
);
blink: process
begin
if one_hz_p ='1' then
tdc_led_status <= '1';
elsif tdc_led_count_done = '1' then
tdc_led_status <= '0';
end if;
wait until clk ='1';
end process;
two_seconds: process
begin
if one_hz_p ='1' then
tdc_led_trig5 <= not(tdc_led_trig5);
end if;
wait until clk ='1';
end process;
spec_led_counter: free_counter spec_led_counter: free_counter
port map( port map(
clk => spec_clk, clk => spec_clk,
...@@ -600,9 +636,6 @@ begin ...@@ -600,9 +636,6 @@ begin
current_value => open current_value => open
); );
spec_led_period <= spec_led_period_sim when values_for_simulation
else spec_led_period_syn;
spec_led: process spec_led: process
begin begin
if gnum_reset ='1' then if gnum_reset ='1' then
...@@ -613,23 +646,19 @@ begin ...@@ -613,23 +646,19 @@ begin
wait until spec_clk ='1'; wait until spec_clk ='1';
end process; end process;
spec_led_period <= spec_led_period_sim when values_for_simulation
else spec_led_period_syn;
tdc_led_period <= tdc_led_period_sim when values_for_simulation
else tdc_led_period_syn;
visible_blink_length <= blink_length_sim when values_for_simulation
else blink_length_syn;
spec_led_green <= pll_ld_i; spec_led_green <= pll_ld_i;
tdc_led_counter: countdown_counter
port map(
clk => clk,
reset => general_reset,
start => one_hz_p,
start_value => visible_blink_length,
count_done => tdc_led_count_done,
current_value => open
);
tdc_led_status <= not(tdc_led_count_done);
-- inputs -- inputs
gnum_reset <= not(rst_n_a_i); gnum_reset <= not(rst_n_a_i) or not(spec_aux1_i);
-- internal signals -- internal signals
acm_adr(19) <= '0'; acm_adr(19) <= '0';
...@@ -640,25 +669,41 @@ begin ...@@ -640,25 +669,41 @@ begin
acm_dat_w <= csr_dat_w; acm_dat_w <= csr_dat_w;
csr_ack(0) <= acm_ack; csr_ack(0) <= acm_ack;
csr_dat_r <= acm_dat_r; csr_dat_r <= acm_dat_r;
-- csr_dat_r <= x"0B0AB0BA";
-- outputs -- outputs
pll_cs_o <= pll_cs; mute_inputs_o <= '1';
mute_inputs_o <= '0';
tdc_led_status_o <= tdc_led_status;
tdc_led_trig1_o <= tdc_led_trig1;
tdc_led_trig2_o <= tdc_led_trig2;
tdc_led_trig3_o <= tdc_led_trig3;
tdc_led_trig4_o <= tdc_led_trig4;
tdc_led_trig5_o <= tdc_led_trig5;
term_en_1_o <= '1'; term_en_1_o <= '1';
term_en_2_o <= '1'; term_en_2_o <= '1';
term_en_3_o <= '1'; term_en_3_o <= '1';
term_en_4_o <= '1'; term_en_4_o <= '1';
term_en_5_o <= '1'; term_en_5_o <= '1';
spec_aux5_o <= spec_aux0_i;
spec_aux4_o <= spec_aux1_i;
button_with_spec_clk: process
begin
spec_aux3_o <= spec_aux0_i;
wait until spec_clk ='1';
end process;
button_with_tdc_clk: process
begin
spec_aux2_o <= spec_aux0_i;
wait until clk ='1';
end process;
spec_led_green_o <= spec_led_green; spec_led_green_o <= spec_led_green;
spec_led_red_o <= spec_led_red; spec_led_red_o <= spec_led_red;
tdc_led_status_o <= tdc_led_status;
tdc_led_trig1_o <= tdc_led_trig1;
tdc_led_trig2_o <= tdc_led_trig2;
tdc_led_trig3_o <= tdc_led_trig3;
tdc_led_trig4_o <= tdc_led_trig4;
tdc_led_trig5_o <= tdc_led_trig5;
-- this is the config for acam test... -- this is the config for acam test...
clock_period <= sim_clock_period when values_for_simulation clock_period <= sim_clock_period when values_for_simulation
else syn_clock_period; else syn_clock_period;
...@@ -668,9 +713,8 @@ begin ...@@ -668,9 +713,8 @@ begin
start_dis_o <= '0'; start_dis_o <= '0';
stop_dis_o <= '0'; stop_dis_o <= '0';
-- when button 1 is pressed --> start every second. Otherwise start with button 0 -- when button 1 is pressed --> start every second. Otherwise start with button 0
start_from_fpga_o <= one_hz_p when spec_aux1_i ='0' else not(spec_aux0_i); start_from_fpga_o <= one_hz_p;-- when spec_aux1_i ='0' else not(spec_aux0_i);
spec_aux2_o <= spec_aux0_i;
spec_aux3_o <= spec_aux1_i;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/spec/src/rtl/test_tdc_pll/top_test_pll.vhd
View file @ b5ae1362
...@@ -356,9 +356,9 @@ begin ...@@ -356,9 +356,9 @@ begin
wait until clk ='1'; wait until clk ='1';
end process; end process;
spec_aux2_o <= pll_sclk; spec_aux2_o <= pll_sdi;
spec_aux3_o <= pll_sdi; spec_aux3_o <= pll_cs;
spec_aux4_o <= pll_cs; spec_aux4_o <= general_reset;
spec_aux5_o <= gnum_reset; spec_aux5_o <= gnum_reset;
end rtl; end rtl;
......
hdl/spec/src/test_bench/tb_tdc.vhd
View file @ b5ae1362
...@@ -531,6 +531,8 @@ begin ...@@ -531,6 +531,8 @@ begin
generic map generic map
( (
STRING_MAX => STRING_MAX, STRING_MAX => STRING_MAX,
-- T_LCLK => 5 ns,
-- T_LCLK => 10 ns,
T_LCLK => 6.25 ns, T_LCLK => 6.25 ns,
T_P2L_CLK_DLY => 2 ns, T_P2L_CLK_DLY => 2 ns,
INSTANCE_LABEL => "U0(Primary GN412x): ", INSTANCE_LABEL => "U0(Primary GN412x): ",
......
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