merged clock tree fixes branch

bf36a0c8 · Tomasz Wlostowski · 7bb56989 · 4d472dcb · bf36a0c8 · bf36a0c8
Commit bf36a0c8 authored Mar 20, 2015 by Tomasz Wlostowski
33 changed files
--- a/.gitignore
+++ b/.gitignore
+*.*\#
+\#*
+.\#*
+*.*~
+hdl/ip_cores/*
+modelsim.ini
+*.wlf
+*.vstf
+work
+*.bak
+syn/*
+transcript
\ No newline at end of file
--- a/Manifest.py
+++ b/Manifest.py
+modules = {"local": [
+	    "hdl/rtl",
+	    "hdl/top/spec"] };
--- a/hdl/platform/xilinx/Manifest.py
+++ b/hdl/platform/xilinx/Manifest.py
+files = [
+    "blk_mem_circ_buff_v6_4.ngc",
+    "blk_mem_gen_v6_1.ngc",
+    "blk_mem_gen_v6_2.ngc",
+    "blk_mem_gen_v6_3.ngc",
+    "Manifest.py"
+]
--- a/hdl/platform/xilinx/blk_mem_circ_buff_v6_4.ngc
+++ b/hdl/platform/xilinx/blk_mem_circ_buff_v6_4.ngc
--- a/hdl/platform/xilinx/blk_mem_gen_v6_1.ngc
+++ b/hdl/platform/xilinx/blk_mem_gen_v6_1.ngc
--- a/hdl/platform/xilinx/blk_mem_gen_v6_2.ngc
+++ b/hdl/platform/xilinx/blk_mem_gen_v6_2.ngc
--- a/hdl/platform/xilinx/blk_mem_gen_v6_3.ngc
+++ b/hdl/platform/xilinx/blk_mem_gen_v6_3.ngc
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
+files = ["acam_databus_interface.vhd",
+"acam_timecontrol_interface.vhd",
+"carrier_info.vhd",
+"circular_buffer.vhd",
+"clks_rsts_manager.vhd",
+"data_engine.vhd",
+"data_formatting.vhd",
+"decr_counter.vhd",
+"fmc_tdc_core.vhd",
+"fmc_tdc_mezzanine.vhd",
+"free_counter.vhd",
+"incr_counter.vhd",
+"irq_generator.vhd",
+"leds_manager.vhd",
+"local_pps_gen.vhd",
+"reg_ctrl.vhd",
+"start_retrig_ctrl.vhd",
+"tdc_eic.vhd",
+"wrabbit_sync.vhd"];
+
--- a/hdl/rtl/circular_buffer.vhd
+++ b/hdl/rtl/circular_buffer.vhd
@@ -105,7 +105,8 @@ entity circular_buffer is
  port
  -- INPUTS
     -- Signal from the clk_rst_manager
-    (clk_i                : in std_logic;                      -- 125 MHz clock; same for both ports
+    (clk_tdc_i                : in std_logic;                      -- 125 MHz clock; same for both ports
+     clk_sys_i : in std_logic;

     -- Signals from the data_formatting unit (WISHBONE classic): timestamps writing
     tstamp_wr_rst_i   : in std_logic;                         -- timestamp writing WISHBONE reset
@@ -155,9 +156,9 @@ begin
 --                            TIMESTAMP WRITINGS WISHBONE CLASSIC ACK                            --
 ---------------------------------------------------------------------------------------------------
  -- WISHBONE classic interface compatible slave
-  classic_interface: process (clk_i)
+  classic_interface: process (clk_tdc_i)
  begin
-    if rising_edge (clk_i) then
+    if rising_edge (clk_tdc_i) then
      if tstamp_wr_rst_i ='1' then
        tstamp_wr_ack_p <= '0';

@@ -186,9 +187,9 @@ begin
 -- ACK : _________________|-----------------------------------|_____
 -- DATO:                  <DAT0><DAT1><DAT2><DAT3><DAT4><DAT5>

-  WB_pipe_ack_fsm_seq: process (clk_i)
+  WB_pipe_ack_fsm_seq: process (clk_sys_i)
  begin
-    if rising_edge (clk_i) then
+    if rising_edge (clk_sys_i) then
      if tdc_mem_wb_rst_i ='1' then
        tstamp_rd_wb_st <= IDLE;
      else
@@ -275,7 +276,7 @@ begin
  memory_block: blk_mem_circ_buff_v6_4
  port map(
    -- Port A: attached to the data_formatting unit
-    clka   => clk_i,
+    clka   => clk_tdc_i,
    addra  => tstamp_wr_adr_i(7 downto 0), -- 2^8 = 256 addresses
    dina   => tstamp_wr_dat_i,             -- 128-bit long timestamps
    ena    => tstamp_wr_cyc_i,
@@ -283,7 +284,7 @@ begin
    douta  => tstamp_wr_dat_o,             -- not used

    -- Port B: attached to the GN4124/VME_core unit
-    clkb   => clk_i,
+    clkb   => clk_sys_i,
    addrb  => tdc_mem_wb_adr_i(9 downto 0),-- 2^10 = 1024 addresses
    dinb   => tdc_mem_wb_dat_i,            -- not used
    enb    => tdc_mem_wb_cyc_i,

--- a/hdl/rtl/data_engine.vhd
+++ b/hdl/rtl/data_engine.vhd
@@ -198,7 +198,7 @@ begin
  data_engine_fsm_comb: process (engine_st, activate_acq_p_i, deactivate_acq_p_i, acam_ef1_i, acam_adr,
                                 acam_ef2_i, acam_ef1_meta_i, acam_ef2_meta_i, acam_wr_config_p_i,
                                 acam_rdbk_config_p_i, acam_rdbk_status_p_i, acam_ack_i, acam_rst_p_i,
-                                 acam_rdbk_ififo1_p_i, acam_rdbk_ififo2_p_i, acam_rdbk_start01_p_i,
+                                 acam_rdbk_ififo1_p_i, acam_rdbk_ififo2_p_i, acam_rdbk_start01_p_i,
 											start_from_fpga_i, time_c, time_c_full_p)
  begin
    case engine_st is
@@ -388,6 +388,8 @@ begin
                        acam_stb        <= '1';
                        acam_we         <= '0';
                  -----------------------------------------------
+                        time_c_en <= '0';
+                        time_c_rst <= '0';

                        if deactivate_acq_p_i = '1' then
                          nxt_engine_st   <= INACTIVE;
@@ -414,7 +416,8 @@ begin
                        acam_cyc        <= '1';
                        acam_stb        <= '1';
                        acam_we         <= '0';
-                  -----------------------------------------------
+                        time_c_en <= '0';
+                        time_c_rst <= '0';                  -----------------------------------------------

                        if deactivate_acq_p_i = '1' then
                          nxt_engine_st   <= INACTIVE;
@@ -441,7 +444,9 @@ begin
                        acam_cyc        <= '1';
                        acam_stb        <= '1';
                        acam_we         <= '1';
-                  -----------------------------------------------
+                        time_c_en <= '0';
+                        time_c_rst <= '0';
+                -----------------------------------------------

                        if acam_ack_i = '1' and acam_adr = x"0E" then  -- last address
                          nxt_engine_st   <= INACTIVE;
@@ -456,7 +461,8 @@ begin
                        acam_cyc        <= '1';
                        acam_stb        <= '1';
                        acam_we         <= '0';
-                  -----------------------------------------------
+                        time_c_en <= '0';
+                        time_c_rst <= '0';                 -----------------------------------------------

                        if acam_ack_i = '1' and acam_adr = x"0E" then  -- last address
                          nxt_engine_st   <= INACTIVE;
@@ -471,7 +477,9 @@ begin
                        acam_cyc        <= '1';
                        acam_stb        <= '1';
                        acam_we         <= '0';
-                  -----------------------------------------------
+                        time_c_en <= '0';
+                        time_c_rst <= '0';                 
+						-----------------------------------------------

                        if acam_ack_i ='1' then
                          nxt_engine_st   <= INACTIVE;
@@ -486,6 +494,8 @@ begin
                        acam_cyc        <= '1';
                        acam_stb        <= '1';
                        acam_we         <= '0';
+                        time_c_en <= '0';
+                        time_c_rst <= '0';
                  -----------------------------------------------

                        if acam_ack_i ='1' then
@@ -501,6 +511,8 @@ begin
                        acam_cyc        <= '1';
                        acam_stb        <= '1';
                        acam_we         <= '0';
+                        time_c_en <= '0';
+                        time_c_rst <= '0';
                  -----------------------------------------------

                        if acam_ack_i ='1' then
@@ -515,6 +527,8 @@ begin
                        acam_cyc        <= '1';
                        acam_stb        <= '1';
                        acam_we         <= '1';
+                        time_c_en <= '0';
+                        time_c_rst <= '0';
                  -----------------------------------------------

                        if acam_ack_i ='1' then
@@ -529,6 +543,8 @@ begin
                        acam_cyc        <= '0';
                        acam_stb        <= '0';
                        acam_we         <= '0';
+                        time_c_en <= '0';
+                        time_c_rst <= '0';
                  -----------------------------------------------

                        nxt_engine_st     <= INACTIVE;

--- a/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/rtl/fmc_tdc_core.vhd
--- a/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/rtl/fmc_tdc_mezzanine.vhd
--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
--- a/hdl/sim/spec/data_vectors/acam_test_cmd0.vec
+++ b/hdl/sim/spec/data_vectors/acam_test_cmd0.vec
+-------------------------------------------------------------------------------
+-- acam_test.vec
+-------------------------------------------------------------------------------
+-- Select the GN4124 Primary BFM
+model 0
+
+-- Initialize the BFM to its default state
+init
+
+-------------------------------------------------------------------------------
+-- Initialize the Primary GN412x BFM model
+-------------------------------------------------------------------------------
+-- These address ranges will generate traffic from the BFM to the FPGA
+-- bar BAR ADDR SIZE VC TC S
+bar     0 0000000000000000 00100000 0 7 0
+
+-- This allocates a RAM block inside the BFM for the FPGA to access
+-- bfm_bar BAR ADDR SIZE
+bfm_bar 0 0000000040000000 20000000
+bfm_bar 1 0000000020000000 20000000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d50000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d60000
+
+-------------------------------------------------------------------------------
+-- Access the tdc core register space
+-------------------------------------------------------------------------------
+-- the following writes will go out in a single packet
+
+-- Gonzalo: 3 writings outside of the BAR defined memory space to check that 
+-- the BFM model does not forward them to the Local bus
+
+wr 0000000040000808 F 0001F04C
+wait   %d50
+wr 0000000040000800 F 00021040
+wait   %d50
+wr 0000000040000800 F 00025000
+wait   %d50
+
+-- Gonzalo: 5 reads inside Matthieu's core memory space to check that the core
+-- does not forward them to the wishbone bus
+
+rd 0000000000000000 F 0000A0A1
+wait   %d20
+rd 0000000000000004 F 0000A0A2
+wait   %d20
+rd 0000000000000008 F 0000A0A3
+wait   %d20
+rd 000000000000000C F 0000A0A4
+wait   %d20
+rd 0000000000000010 F 0000A0A5
+wait   %d60
+
+-- Gonzalo: actual wr and rd for test
+
+wr 0000000000005000 F 0000FC81
+wait   %d50
+wr 000000000000502C F 00FF0000
+wait   %d50
+rd 0000000000080000 F 0000FC81
+wait   %d50
+rd 000000000008002C F 00FF0000
+wait   %d50
+
+wr 0000000000080030 F 04000000
+wait   %d50
+rd 0000000000080030 F 04000000
+wait   %d50
--- a/hdl/sim/spec/data_vectors/atdc_test_cmd0.vec
+++ b/hdl/sim/spec/data_vectors/atdc_test_cmd0.vec
@@ -54,97 +54,126 @@ wait   %d60000

 -- Gonzalo: actual wr and rd on the application memory space for test
 -- writing stuff on the TDC config
--wr 0000000000051000 F 00000040
+--wr 0000000000005000 F 00000040
 --wait   %d20
--wr 0000000000051004 F 00000000
+--wr 0000000000005004 F 00000000
 --wait   %d20
--wr 0000000000051008 F 00000000
+--wr 0000000000005008 F 00000000
 --wait   %d60

 -- writing stuff for the ACAM config
-wr 0000000000051000 F 01F0FC81
+wr 0000000000005000 F 01F0FC81
 wait   %d20
-wr 0000000000051004 F 00000000
+wr 0000000000005004 F 00000000
 wait   %d20
-wr 0000000000051008 F 00000E02
+wr 0000000000005008 F 00000E02
 wait   %d60

 -- loading the utc time
-wr 00000000000510FC F 00000200
+wr 00000000000050FC F 00000200
 wait   %d200

 -- loading the acam config
-wr 000000000005100FC F 00000004
+wr 00000000000050FC F 00000004
 wait   %d200

 -- reading back the acam config
-wr 00000000000510FC F 00000008
+wr 00000000000050FC F 00000008
 wait   %d200

 -- activate acquisition
-wr 00000000000510FC F 00000001
+wr 00000000000050FC F 00000001
 wait   %d540000

 -- read circular buffer wr pointer
-rd 00000000000510A8 F 00000000
+rd 000000000000509C F 00000000
 wait   %d200

-
-- deactivate acquisition
-wr 00000000000510FC F 00000002
-wait   %d200
-
-
-- read a timestamps from memory
-rd 0000000000054000 F 00000000
-wait   %d100
-rd 0000000000054004 F 00000000
-wait   %d100
-rd 0000000000054008 F 00000000
+-- prepare and launch DMA transfer
+wr 000000000000000C F 36EF8000
+wait   %d20
+wr 0000000000000014 F 00000210
 wait   %d100
-rd 000000000005400C F 00000000
+
+wr 0000000000000000 F 00000001
 wait   %d100


+-- deactivate acquisition
+wr 00000000000800FC F 00000002
+wait   %d200
+
 -- read acam status
-wr 00000000000510FC F 00000010
+wr 00000000000800FC F 00000010
 wait   %d100
-rd 0000000000051070 F 00000000
+rd 0000000000080070 F 00000000
 wait   %d100

 -- read acam ififo1
-wr 00000000000510FC F 00000020
+wr 00000000000800FC F 00000020
 wait   %d100
-rd 0000000000051060 F 00000000
+rd 0000000000080060 F 00000000
 wait   %d100

 -- read acam ififo2
-wr 00000000000510FC F 00000040
+wr 00000000000800FC F 00000040
 wait   %d100
-rd 0000000000051064 F 00000000
+rd 0000000000080064 F 00000000
 wait   %d100

 -- read acam start01 register
-wr 00000000000510FC F 00000080
+wr 00000000000800FC F 00000080
 wait   %d100
-rd 0000000000051068 F 00000000
+rd 0000000000080068 F 00000000
 wait   %d100

 -- reset acam
-wr 00000000000510FC F 00000100
+wr 00000000000800FC F 00000100
 wait   %d200

--rd 0000000000051000 F 00001234
+--rd 0000000000080000 F 00001234
 --wait   %d20
--rd 0000000000051004 F 00005678
+--rd 0000000000080004 F 00005678
 --wait   %d20
--rd 0000000000051008 F 0000abcd
+--rd 0000000000080008 F 0000abcd
 --wait   %d20
--rd 000000000005100C F 0000ef90
+--rd 000000000008000C F 0000ef90
 --wait   %d60
 --
--wr 00000000000510FC F 00000001
+--wr 00000000000800FC F 00000001
 --wait   %d100
--wr 00000000000510FC F 00000002
+--wr 00000000000800FC F 00000002
 --wait   %d100

+
+
+
+
+---- Gonzalo: registers inside Matthieu's core memory space are written with the
+---- settings for DMA transfer
+--
+---- Start address on the carrier local memory
+--wr 0000000000000008 F 00000000
+--wait   %d20
+--
+---- Start addresses on the PCI host memory
+--wr 000000000000000C F 0000A0A4
+--wait   %d20
+--wr 0000000000000010 F 0000A0A5
+--wait   %d20
+--
+---- Transfer length
+--wr 0000000000000014 F 00000060
+--wait   %d20
+--
+---- Chain control
+--wr 0000000000000020 F 00000000
+--wait   %d60
+--
+---- Start transfer through the Control register and check through the status register
+--wr 0000000000000000 F 00000001
+--wait   %d100
+--rd 0000000000000004 F 00000001
+--wait   %d100
+--
+--
--- a/hdl/sim/spec/data_vectors/memo_test_cmd0.vec
+++ b/hdl/sim/spec/data_vectors/memo_test_cmd0.vec
+-------------------------------------------------------------------------------
+-- acam_test.vec
+-------------------------------------------------------------------------------
+-- Select the GN4124 Primary BFM
+model 0
+
+-- Initialize the BFM to its default state
+init
+
+-------------------------------------------------------------------------------
+-- Initialize the Primary GN412x BFM model
+-------------------------------------------------------------------------------
+-- These address ranges will generate traffic from the BFM to the FPGA
+-- bar BAR ADDR SIZE VC TC S
+bar     0 0000000000000000 00100000 0 7 0
+
+-- This allocates a RAM block inside the BFM for the FPGA to access
+-- bfm_bar BAR ADDR SIZE
+bfm_bar 0 0000000040000000 20000000
+bfm_bar 1 0000000020000000 20000000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d50000
+
+-- Drive reset to the FPGA
+reset %d320
+-- Wait until the FPGA is un-reset and ready for traffic on the local bus
+wait   %d60000
+
+-------------------------------------------------------------------------------
+-- Access the tdc core register space
+-------------------------------------------------------------------------------
+-- the following writes will go out in a single packet
+
+-- Gonzalo: 3 writings outside of the BAR defined memory space to check that 
+-- the BFM model does not forward them to the Local bus
+
+wr 0000000040000808 F 0001F04C
+wait   %d20
+wr 0000000040000800 F 00021040
+wait   %d20
+wr 0000000040000800 F 00025000
+wait   %d60
+
+-- Gonzalo: 3 reads inside Matthieu's core memory space to check that the core
+-- does not forward them to the wishbone bus
+
+rd 0000000000000000 F 0000A0A1
+wait   %d20
+rd 0000000000000004 F 0000A0A2
+wait   %d20
+rd 0000000000000008 F 0000A0A3
+wait   %d60
+
+-- Gonzalo: actual wr and rd on the application memory space for test
+
+wr 0000000000080000 F 00001234
+wait   %d20
+wr 0000000000080004 F 00005678
+wait   %d20
+wr 0000000000080008 F 0000abcd
+wait   %d20
+wr 000000000008000C F 0000ef90
+wait   %d60
+
+rd 0000000000080000 F 00001234
+wait   %d20
+rd 0000000000080004 F 00005678
+wait   %d20
+rd 0000000000080008 F 0000abcd
+wait   %d20
+rd 000000000008000C F 0000ef90
+wait   %d60
+
+wr 0000000000080100 F 00000001
+wait   %d100
+wr 0000000000080100 F 00000002
+wait   %d100
+
+-- Gonzalo: registers inside Matthieu's core memory space are written with the
+-- settings for DMA transfer
+
+-- Start address on the carrier local memory
+wr 0000000000000008 F 00000000
+wait   %d20
+
+-- Start addresses on the PCI host memory
+wr 000000000000000C F 0000A0A4
+wait   %d20
+wr 0000000000000010 F 0000A0A5
+wait   %d20
+
+-- Transfer length
+wr 0000000000000014 F 00000060
+wait   %d20
+
+-- Chain control
+wr 0000000000000020 F 00000000
+wait   %d60
+
+-- Start transfer through the Control register and check through the status register
+wr 0000000000000000 F 00000001
+wait   %d100
+rd 0000000000000004 F 00000001
+wait   %d100
+
--- a/hdl/sim/spec/spec_fmc_tdc_sim.xise
+++ b/hdl/sim/spec/spec_fmc_tdc_sim.xise
--- a/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise
+++ b/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise
--- a/hdl/syn/spec/xilinx/spec_top_fmc_tdc/wrc.ram
+++ b/hdl/syn/spec/xilinx/spec_top_fmc_tdc/wrc.ram
--- a/hdl/testbench/spec/tb_tdc.vhd
+++ b/hdl/testbench/spec/tb_tdc.vhd
@@ -26,7 +26,7 @@ end tb_tdc;

 architecture behavioral of tb_tdc is

-    component spec_top_fmc_tdc
+    component top_tdc
    generic(
        g_span                  : integer :=32;
        g_width                 : integer :=32;
@@ -34,8 +34,7 @@ architecture behavioral of tb_tdc is
    );
    port(
        -- interface with GNUM circuit
-        rst_n_a_i      : in  std_logic;
-		  spec_clk_i     : in  std_logic;
+        rst_n_a_i      : in  std_logic;
        -- P2L Direction
        p2l_clk_p_i : in  std_logic;                      -- Receiver Source Synchronous Clock+
        p2l_clk_n_i : in  std_logic;                      -- Receiver Source Synchronous Clock-
@@ -61,7 +60,7 @@ architecture behavioral of tb_tdc is
        irq_p_o     : out std_logic;                      -- Interrupt request pulse to GN4124 GPIO

       -- interface signals with PLL circuit
-        acam_refclk_p_i           : in std_logic;
+        acam_refclk_p_i           : in std_logic;
        acam_refclk_n_i           : in std_logic;
        --pll_ld_i                : in std_logic;
        --pll_refmon_i            : in std_logic;
@@ -72,8 +71,8 @@ architecture behavioral of tb_tdc is
        pll_dac_sync_o          : out std_logic;
        pll_sdi_o               : out std_logic;
        pll_sclk_o              : out std_logic;
-        tdc_clk_125m_p_i             : in std_logic;
-        tdc_clk_125m_n_i             : in std_logic;
+        tdc_clk_p_i             : in std_logic;
+        tdc_clk_n_i             : in std_logic;

        -- interface signals with acam (timing)
        err_flag_i              : in std_logic;
@@ -113,11 +112,23 @@ architecture behavioral of tb_tdc is
        tdc_led_trig5_o         : out std_logic;

        carrier_one_wire_b      : inout std_logic;
-        mezz_sys_scl_b          : inout std_logic;
-        mezz_sys_sda_b          : inout std_logic;
+        sys_scl_b               : inout std_logic;
+        sys_sda_b               : inout std_logic;
        mezz_one_wire_b         : inout std_logic;
        pcb_ver_i               : in std_logic_vector(3 downto 0);
-        prsnt_m2c_n_i           : in std_logic);
+        prsnt_m2c_n_i           : in std_logic;
+
+        -- other signals on the spec card
+        spec_aux0_i             : in std_logic;
+        spec_aux1_i             : in std_logic;
+        spec_aux2_o             : out std_logic;
+        spec_aux3_o             : out std_logic;
+        spec_aux4_o             : out std_logic;
+        spec_aux5_o             : out std_logic;
+        spec_led_green_o        : out std_logic;
+        spec_led_red_o          : out std_logic;
+        spec_clk_i              : in std_logic
+    );
    end component;

    component acam_model
@@ -284,7 +295,7 @@ constant start_retrig_period    : time:= 512 ns;
  -- Maximum width of a command string
  constant STRING_MAX : integer                      := 256;

-signal acam_refclk_i        : std_logic:='0';
+signal acam_refclk_i        : std_logic:='0';
 signal acam_refclk_n_i      : std_logic:='1';
 signal tdc_clk_p_i          : std_logic:='0';
 signal tdc_clk_n_i          : std_logic:='1';
@@ -387,7 +398,7 @@ signal spare                : std_logic;

 begin

-    dut: spec_top_fmc_tdc
+    dut: top_tdc
    generic map(
        g_span                  => 32,
        g_width                 => 32,
@@ -395,8 +406,7 @@ begin
    )
    port map(
        -- interface with GNUM circuit
-        rst_n_a_i               => rst_n,
-		  spec_clk_i              => spec_clk_i,
+        rst_n_a_i               => rst_n,
        p2l_clk_p_i             => p2l_clkp,
        p2l_clk_n_i             => p2l_clkn,
        p2l_data_i              => p2l_data,
@@ -420,7 +430,7 @@ begin
        irq_p_o                 => irq_p,
        
        -- interface with PLL circuit
-        acam_refclk_p_i         => acam_refclk_i,
+        acam_refclk_p_i         => acam_refclk_i,
        acam_refclk_n_i         => acam_refclk_n_i,
        --pll_ld_i                => pll_ld_i,
        --pll_refmon_i            => pll_refmon_i,
@@ -431,8 +441,8 @@ begin
        pll_dac_sync_o          => pll_dac_sync_o,
        pll_sdi_o               => pll_sdi_o,
        pll_sclk_o              => pll_sclk_o,
-        tdc_clk_125m_p_i	     => tdc_clk_p_i,
-        tdc_clk_125m_n_i	     => tdc_clk_n_i,
+        tdc_clk_p_i	            => tdc_clk_p_i,
+        tdc_clk_n_i	            => tdc_clk_n_i,
        
        -- interface signals with acam (timing)
        int_flag_i          => int_flag_i,
@@ -473,11 +483,21 @@ begin
       
        -- other signals on the spec card
        carrier_one_wire_b  => open,
-        mezz_sys_scl_b      => open,
-        mezz_sys_sda_b      => open,
+        sys_scl_b           => open,
+        sys_sda_b           => open,
        mezz_one_wire_b     => open,
        pcb_ver_i           => (others => '0'),
-        prsnt_m2c_n_i       => '1');
+        prsnt_m2c_n_i       => '0',
+        spec_aux0_i         => spec_aux0_i,
+        spec_aux1_i         => spec_aux1_i,
+        spec_aux2_o         => spec_aux2_o,
+        spec_aux3_o         => spec_aux3_o,
+        spec_aux4_o         => spec_aux4_o,
+        spec_aux5_o         => spec_aux5_o,
+        spec_led_green_o    => spec_led_green,
+        spec_led_red_o      => spec_led_red,
+        spec_clk_i          => spec_clk_i
+    );
    
    acam: acam_model
    generic map(
@@ -645,8 +665,8 @@ begin
        end if;
        wait for pll_clk_period*2;
    end process;
-    acam_refclk_n_i <= not acam_refclk_i;
-
+    acam_refclk_n_i <= not acam_refclk_i;
+
    
    spec_clock: process
    begin

--- a/hdl/top/spec/Manifest.py
+++ b/hdl/top/spec/Manifest.py
+files = ["fmc_tdc_wrapper.vhd",
+	 "tdc_core_pkg.vhd",
+         "fmc_tdc_direct_readout.vhd",
+         "fmc_tdc_direct_readout_slave.vhd",
+         "fmc_tdc_direct_readout_slave_pkg.vhd"
+];
+
+modules = {"local" : [ "../../platform/xilinx" ] }
+
--- a/hdl/top/spec/build_wb.sh
+++ b/hdl/top/spec/build_wb.sh
+#!/bin/bash
+
+wbgen2  -D 1.html -V fmc_tdc_direct_readout_slave.vhd -H record -p fmc_tdc_direct_readout_slave_pkg.vhd -K regs.vh -s defines -C fmctdc-direct.h fmc_tdc_direct_readout_slave.wb
--- a/hdl/top/spec/fmc_tdc_direct_readout.vhd
+++ b/hdl/top/spec/fmc_tdc_direct_readout.vhd
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+use work.tdc_core_pkg.all;
+use work.wishbone_pkg.all;
+use work.dr_wbgen2_pkg.all;
+
+entity fmc_tdc_direct_readout is
+  port
+    (
+      clk_tdc_i   : in std_logic;
+      rst_tdc_n_i : in std_logic;
+
+      clk_sys_i   : in std_logic;
+      rst_sys_n_i : in std_logic;
+
+      direct_timestamp_i    : in std_logic_vector(127 downto 0);
+      direct_timestamp_wr_i : in std_logic;
+
+      direct_slave_i : in  t_wishbone_slave_in;
+      direct_slave_o : out t_wishbone_slave_out
+      );
+
+end entity;
+
+
+architecture rtl of fmc_tdc_direct_readout is
+
+  component fmc_tdc_direct_readout_wb_slave is
+    port (
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(2 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      clk_tdc_i  : in  std_logic;
+      regs_i     : in  t_dr_in_registers;
+      regs_o     : out t_dr_out_registers);
+  end component fmc_tdc_direct_readout_wb_slave;
+
+  constant c_num_channels : integer := 5;
+
+  type t_channel_state is record
+    enable  : std_logic;
+    timeout : unsigned(23 downto 0);
+    fifo_wr : std_logic;
+  end record;
+
+  type t_channel_state_array is array(0 to c_num_channels-1) of t_channel_state;
+
+  signal c : t_channel_state_array;
+
+  signal regs_out : t_dr_out_registers;
+  signal regs_in  : t_dr_in_registers;
+
+  signal ts_cycles  : std_logic_vector(31 downto 0);
+  signal ts_seconds : std_logic_vector(31 downto 0);
+  signal ts_bins    : std_logic_vector(17 downto 0);
+  signal ts_edge    : std_logic;
+  signal ts_channel : std_logic_vector(2 downto 0);
+
+  signal direct_slave_out: t_wishbone_slave_out;
+  
+begin
+
+
+  ts_channel <= direct_timestamp_i(98 downto 96);
+  ts_edge    <= direct_timestamp_i(100);
+  ts_seconds <= direct_timestamp_i(95 downto 64);
+  ts_cycles  <= direct_timestamp_i(63 downto 32);
+  ts_bins    <= direct_timestamp_i(17 downto 0);
+
+  U_WB_Slave : fmc_tdc_direct_readout_wb_slave
+    port map (
+      rst_n_i    => rst_sys_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => direct_slave_i.adr(4 downto 2),
+      wb_dat_i   => direct_slave_i.dat,
+      wb_dat_o   => direct_slave_out.dat,
+      wb_cyc_i   => direct_slave_i.cyc,
+      wb_sel_i   => direct_slave_i.sel,
+      wb_stb_i   => direct_slave_i.stb,
+      wb_we_i    => direct_slave_i.we,
+      wb_ack_o   => direct_slave_out.ack,
+      wb_stall_o => direct_slave_out.stall,
+      clk_tdc_i  => clk_tdc_i,
+      regs_i     => regs_in,
+      regs_o     => regs_out);
+
+  direct_slave_out.err <= '0';
+  direct_slave_out.rty <= '0';
+
+  direct_slave_o <= direct_slave_out;
+
+  regs_in.fifo_cycles_i  <= ts_cycles;
+  regs_in.fifo_edge_i    <= '1';
+  regs_in.fifo_seconds_i <= ts_seconds;
+  regs_in.fifo_channel_i <= '0'&ts_channel;
+  regs_in.fifo_bins_i    <= ts_bins;
+
+
+  gen_channels : for i in 0 to c_num_channels-1 generate
+
+    p_dead_time : process (clk_tdc_i)
+    begin
+      if rising_edge(clk_tdc_i) then
+        if rst_tdc_n_i = '0' then
+          c(i).timeout <= (others => '0');
+          c(i).enable  <= '0';
+          c(i).fifo_wr <= '0';
+        else
+          c(i).enable <= regs_out.chan_enable_o(i);
+
+          if c(i).enable = '1' then
+            if direct_timestamp_wr_i = '1' and unsigned(ts_channel) = i and ts_edge = '1' and c(i).timeout = 0 then
+              c(i).timeout <= unsigned(regs_out.dead_time_o);
+              c(i).fifo_wr <= '1';
+            elsif c(i).timeout /= 0 then
+              c(i).fifo_wr <= '0';
+              c(i).timeout <= c(i).timeout - 1;
+            end if;
+            
+          else
+            c(i).fifo_wr <= '0';
+            c(i).timeout <= (others => '0');
+          end if;
+        end if;
+      end if;
+    end process;
+    
+  end generate gen_channels;
+
+  p_fifo_write : process(clk_tdc_i)
+  begin
+    if rising_edge(clk_tdc_i) then
+      if rst_tdc_n_i = '0' then
+        regs_in.fifo_wr_req_i <= '0';
+      else
+        regs_in.fifo_wr_req_i <= '0';
+
+        for i in 0 to c_num_channels-1 loop
+          if(c(i).fifo_wr = '1' and regs_out.fifo_wr_full_o = '0') then
+            regs_in.fifo_wr_req_i <= '1';
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process;
+
+end rtl;
+
+
--- a/hdl/top/spec/fmc_tdc_direct_readout_slave.vhd
+++ b/hdl/top/spec/fmc_tdc_direct_readout_slave.vhd
--- a/hdl/top/spec/fmc_tdc_direct_readout_slave.wb
+++ b/hdl/top/spec/fmc_tdc_direct_readout_slave.wb
--- a/hdl/top/spec/fmc_tdc_direct_readout_slave_pkg.vhd
+++ b/hdl/top/spec/fmc_tdc_direct_readout_slave_pkg.vhd
--- a/hdl/top/spec/fmc_tdc_wrapper.vhd
+++ b/hdl/top/spec/fmc_tdc_wrapper.vhd
--- a/hdl/top/spec/sdb_meta_pkg.vhd
+++ b/hdl/top/spec/sdb_meta_pkg.vhd
--- a/hdl/top/spec/spec_reset_gen.vhd
+++ b/hdl/top/spec/spec_reset_gen.vhd
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.gencores_pkg.all;
+
+entity spec_reset_gen is
+  
+  port (
+    clk_sys_i : in std_logic;
+
+    rst_pcie_n_a_i   : in std_logic;
+    rst_button_n_a_i : in std_logic;
+
+    rst_n_o : out std_logic
+    );
+
+end spec_reset_gen;
+
+architecture behavioral of spec_reset_gen is
+
+  signal powerup_cnt     : unsigned(7 downto 0) := x"00";
+  signal button_synced_n : std_logic;
+  signal pcie_synced_n   : std_logic;
+  signal powerup_n       : std_logic            := '0';
+
+begin  -- behavioral
+
+  U_EdgeDet_PCIe : gc_sync_ffs port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => '1',
+    data_i   => rst_pcie_n_a_i,
+    ppulse_o => pcie_synced_n);
+
+  U_Sync_Button : gc_sync_ffs port map (
+    clk_i    => clk_sys_i,
+    rst_n_i  => '1',
+    data_i   => rst_button_n_a_i,
+    synced_o => button_synced_n);
+
+  p_powerup_reset : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if(powerup_cnt /= x"ff") then
+        powerup_cnt <= powerup_cnt + 1;
+        powerup_n   <= '0';
+      else
+        powerup_n <= '1';
+      end if;
+    end if;
+  end process;
+
+  rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
+
+end behavioral;
--- a/hdl/top/spec/spec_top_fmc_tdc.ucf
+++ b/hdl/top/spec/spec_top_fmc_tdc.ucf
--- a/hdl/top/spec/spec_top_fmc_tdc.vhd
+++ b/hdl/top/spec/spec_top_fmc_tdc.vhd
--- a/hdl/top/spec/synthesis_descriptor.vhd
+++ b/hdl/top/spec/synthesis_descriptor.vhd
--- a/hdl/top/spec/tdc_core_pkg.vhd
+++ b/hdl/top/spec/tdc_core_pkg.vhd