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FMC TDC 1ns 5cha - Gateware
Commit c20e2e0e authored by egousiou's avatar egousiou
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no dma (still needs some cleaning) 

git-svn-id: http://svn.ohwr.org/fmc-tdc@149 85dfdc96-de2c-444c-878d-45b388be74a9
parent d463d198
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hdl/syn/spec/syn_tdc.edf
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hdl/syn/spec/syn_tdc.ncf
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......@@ -127,11 +127,11 @@ NET "tdc_led_trig2_o" LOC="B20" ;
NET "tdc_led_trig3_o" LOC="A20" ;
NET "tdc_led_trig4_o" LOC="D17" ;
NET "tdc_led_trig5_o" LOC="C18" ;
NET "mezz_sys_scl_b" LOC="F7" ;
NET "mezz_sys_sda_b" LOC="F8" ;
NET "mezz_one_wire_b" LOC="A19" ;
NET "spec_clk_i" LOC="H12" ;
NET "carrier_one_wire_b" LOC="D4" ;
NET "sys_scl_b" LOC="F7" ;
NET "sys_sda_b" LOC="F8" ;
NET "mezz_one_wire_b" LOC="A19" ;
NET "pcb_ver_i(0)" LOC="P5" ;
NET "pcb_ver_i(1)" LOC="P4" ;
NET "pcb_ver_i(2)" LOC="AA2" ;
......
hdl/syn/spec/synplicity.ucf
View file @ c20e2e0e
......@@ -12,10 +12,10 @@
NET "acam_refclk_p_i" TNM_NET = "acam_refclk_p_i";
TIMESPEC "TS_acam_refclk_p_i" = PERIOD "acam_refclk_p_i" 32.000 ns HIGH 50.00%;
# 1004 : define_clock {n:gnum_interface_block.cmp_clk_in.rx_bufg_pll_x1} -name {gnum_clk200} -freq {200} -clockgroup {default_clkgroup31__4}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "gnum_interface_block.sys_clk" TNM_NET = "gnum_interface_block_sys_clk";
TIMESPEC "TS_gnum_interface_block_sys_clk" = PERIOD "gnum_interface_block_sys_clk" 5.000 ns HIGH 50.00%;
# 1233 : define_clock {n:cmp_GN4124.cmp_clk_in.buf_P_clk} -name {serdes_1_to_n_clk_pll_s2_diff_work_spec_top_fmc_tdc_rtl_6layer0|buf_P_clk_inferred_clock} -ref_rise {0.000000} -ref_fall {2.500000} -uncertainty {0.000000} -period {5.000000} -clockgroup {Inferred_clkgroup_0} -rise {0.000000} -fall {2.500000}
NET "cmp_GN4124.cmp_clk_in.buf_P_clk" TNM_NET = "cmp_GN4124_cmp_clk_in_buf_P_clk";
TIMESPEC "TS_cmp_GN4124_cmp_clk_in_buf_P_clk" = PERIOD "cmp_GN4124_cmp_clk_in_buf_P_clk" 5.000 ns HIGH 50.00%;
# 1002 : define_clock {p:spec_clk_i} -name {spec_clk20} -freq {20} -clockgroup {default_clkgroup29__2}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
......@@ -29,70 +29,55 @@ TIMESPEC "TS_tdc_clk_p_i" = PERIOD "tdc_clk_p_i" 8.000 ns HIGH 50.00%;
#End clock constraints
# 1018 : define_false_path -to {p:tdc_led_status_o}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_status_o" TNM = "to_1018_0";
TIMESPEC "TS_1018_0" = TO "to_1018_0" TIG;
# 1019 : define_false_path -to {p:tdc_led_trig1_o}
# 1007 : define_false_path -to {p:tdc_led_status_o}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig1_o" TNM = "to_1019_0";
TIMESPEC "TS_1019_0" = TO "to_1019_0" TIG;
NET "tdc_led_status_o" TNM = "to_1007_0";
TIMESPEC "TS_1007_0" = TO "to_1007_0" TIG;
# 1020 : define_false_path -to {p:tdc_led_trig2_o}
# 1008 : define_false_path -to {p:tdc_led_trig1_o}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig2_o" TNM = "to_1020_0";
TIMESPEC "TS_1020_0" = TO "to_1020_0" TIG;
NET "tdc_led_trig1_o" TNM = "to_1008_0";
TIMESPEC "TS_1008_0" = TO "to_1008_0" TIG;
# 1021 : define_false_path -to {p:tdc_led_trig3_o}
# 1009 : define_false_path -to {p:tdc_led_trig2_o}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig3_o" TNM = "to_1021_0";
TIMESPEC "TS_1021_0" = TO "to_1021_0" TIG;
NET "tdc_led_trig2_o" TNM = "to_1009_0";
TIMESPEC "TS_1009_0" = TO "to_1009_0" TIG;
# 1022 : define_false_path -to {p:tdc_led_trig4_o}
# 1010 : define_false_path -to {p:tdc_led_trig3_o}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig4_o" TNM = "to_1022_0";
TIMESPEC "TS_1022_0" = TO "to_1022_0" TIG;
NET "tdc_led_trig3_o" TNM = "to_1010_0";
TIMESPEC "TS_1010_0" = TO "to_1010_0" TIG;
# 1023 : define_false_path -to {p:tdc_led_trig5_o}
# 1011 : define_false_path -to {p:tdc_led_trig4_o}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "tdc_led_trig5_o" TNM = "to_1023_0";
TIMESPEC "TS_1023_0" = TO "to_1023_0" TIG;
NET "tdc_led_trig4_o" TNM = "to_1011_0";
TIMESPEC "TS_1011_0" = TO "to_1011_0" TIG;
# 1024 : define_false_path -from {p:rst_n_a_i}
# 1012 : define_false_path -to {p:tdc_led_trig5_o}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
NET "rst_n_a_i" TNM = "from_1024_0";
TIMESPEC "TS_1024_0" = FROM "from_1024_0" TIG;
NET "tdc_led_trig5_o" TNM = "to_1012_0";
TIMESPEC "TS_1012_0" = TO "to_1012_0" TIG;
# 1025 : define_false_path -from {i:gnum_interface_block.rst_reg}
# 1013 : define_false_path -from {p:rst_n_a_i}
# c:\ohwr-fmc-tdc\hdl\syn\spec\tdc_syn_constraints.sdc
INST "gnum_interface_block.rst_reg" TNM = "from_1025_0";
TIMESPEC "TS_1025_0" = FROM "from_1025_0" TIG;
NET "rst_n_a_i" TNM = "from_1013_0";
TIMESPEC "TS_1013_0" = FROM "from_1013_0" TIG;
# Unused constraints (intentionally commented out)
# define_multicycle_path -from { p:data_bus_io[27:0] } { 3 }
# define_multicycle_path -to { p:data_bus_io[27:0] } { 3 }
# define_multicycle_path -to { p:address_o[3:0] } { 3 }
# define_false_path -from { p:spec_aux0_i }
# define_false_path -from { p:spec_aux1_i }
# define_false_path -to { p:spec_aux2_o }
# define_false_path -to { p:spec_aux3_o }
# define_false_path -to { p:spec_aux4_o }
# define_false_path -to { p:spec_aux5_o }
# define_false_path -to { p:spec_led_green_o }
# define_false_path -to { p:spec_led_red_o }
# define_false_path -from { i:gnum_interface_block.rst_reg }
# Location Constraints
PIN "svec_clk_ibuf_cb.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "cmp_GN4124.cmp_clk_in.bufg_135.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "cmp_tdc_clks_rsts_mgment.tdc_clk125_gbuf.O" CLOCK_DEDICATED_ROUTE = FALSE;
# End of generated constraints
hdl/syn/spec/tdc.bin
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hdl/syn/spec/tdc.bit
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hdl/syn/spec/tdc_par_script.tcl
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cd <to the synthesis directory: hdl/syn/spec>
ngdbuild -uc synplicity.ucf syn_tdc.edf
map -detail -w -timing -ol high syn_tdc.ngd
par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
map -detail -xe n -w -timing -ol high syn_tdc.ngd
par -w -xe n -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf
trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report
#bitgen -w par_tdc.ncd tdc
bitgen -w -g Binary:Yes par_tdc.ncd tdc
ngdbuild -uc synplicity.ucf syn_tdc.edf;map -detail -w -timing -ol -pr b high syn_tdc.ngd;par -w -ol high syn_tdc.ncd par_tdc.ncd syn_tdc.pcf;bitgen -w -g Binary:Yes par_tdc.ncd tdc
ngdbuild -uc synplicity.ucf syn_tdc.edf;map -detail -xe n -w -timing -ol high -pr b syn_tdc.ngd;par -w -ol high -xe n -mt off syn_tdc.ncd par_tdc.ncd syn_tdc.pcf;trce -v 32 -u par_tdc.ncd syn_tdc.pcf -o timing_report;bitgen -w -g Binary:Yes par_tdc.ncd tdc
\ No newline at end of file
hdl/syn/spec/tdc_syn.prj
View file @ c20e2e0e
......@@ -69,7 +69,7 @@ add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/wb_vic.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/wb_vic/xwb_vic.vhd"
add_file -vhdl -lib work "../../ip_cores/wishbone/carrier_csr.vhd"
add_file -vhdl -lib work "../../rtl/carrier_info.vhd"
add_file -vhdl -lib work "../../rtl/fmc_tdc_core.vhd"
......@@ -90,8 +90,7 @@ add_file -vhdl -lib work "../../rtl/irq_generator.vhd"
add_file -vhdl -lib work "../../rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../../rtl/leds_manager.vhd"
add_file -vhdl -lib work "../../top/spec/dma_eic.vhd"
add_file -vhdl -lib work "../../top/spec/top_tdc.vhd"
add_file -vhdl -lib work "../../top/spec/spec_top_fmc_tdc.vhd"
add_file -constraint -lib work "./tdc_syn_constraints.sdc"
......@@ -122,7 +121,7 @@ set_option -no_sequential_opt 0
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
set_option -top_module "spec_top_fmc_tdc"
# mapper_options
set_option -frequency 200
......
hdl/syn/spec/tdc_syn_constraints.sdc
View file @ c20e2e0e
......@@ -32,17 +32,6 @@ define_output_delay -disable -default 2.00 -improve 0.00 -route 0.00 -ref {
#
# Delay Paths
#
define_multicycle_path -from {{p:data_bus_io[27:0]}} 3
define_multicycle_path -to {{p:data_bus_io[27:0]}} 3
define_multicycle_path -to {{p:address_o[3:0]}} 3
define_false_path -from {{p:spec_aux0_i}}
define_false_path -from {{p:spec_aux1_i}}
define_false_path -to {{p:spec_aux2_o}}
define_false_path -to {{p:spec_aux3_o}}
define_false_path -to {{p:spec_aux4_o}}
define_false_path -to {{p:spec_aux5_o}}
define_false_path -to {{p:spec_led_green_o}}
define_false_path -to {{p:spec_led_red_o}}
define_false_path -to {{p:tdc_led_status_o}}
define_false_path -to {{p:tdc_led_trig1_o}}
define_false_path -to {{p:tdc_led_trig2_o}}
......@@ -79,7 +68,6 @@ define_attribute {p:pll_sclk_o} {syn_loc} {AA16}
define_attribute {p:pll_dac_sync_o} {syn_loc} {AB16}
define_attribute {p:pll_cs_o} {syn_loc} {Y17}
define_attribute {p:cs_n_o} {syn_loc} {AB17}
define_attribute {p:prsnt_m2c_n_i} {syn_loc} {AB14}
define_attribute {p:err_flag_i} {syn_loc} {V11}
define_attribute {p:int_flag_i} {syn_loc} {W11}
define_attribute {p:start_dis_o} {syn_loc} {T15}
......@@ -192,8 +180,8 @@ define_attribute {p:spec_led_red_o} {syn_loc} {D5}
define_attribute {p:spec_clk_i} {syn_loc} {H12}
define_attribute {p:carrier_one_wire_b} {syn_loc} {D4}
define_attribute {p:mezz_one_wire_b} {syn_loc} {A19}
define_attribute {p:sys_scl_b} {syn_loc} {F7}
define_attribute {p:sys_sda_b} {syn_loc} {F8}
define_attribute {p:mezz_sys_scl_b} {syn_loc} {F7}
define_attribute {p:mezz_sys_sda_b} {syn_loc} {F8}
define_attribute {p:pcb_ver_i[0]} {syn_loc} {P5}
define_attribute {p:pcb_ver_i[1]} {syn_loc} {P4}
define_attribute {p:pcb_ver_i[2]} {syn_loc} {AA2}
......@@ -224,7 +212,6 @@ define_io_standard {pll_sclk_o} syn_pad_type {LVCMOS_25}
define_io_standard {pll_dac_sync_o} syn_pad_type {LVCMOS_25}
define_io_standard {pll_cs_o} syn_pad_type {LVCMOS_25}
define_io_standard {cs_n_o} syn_pad_type {LVCMOS_25}
define_io_standard {prsnt_m2c_n_i} syn_pad_type {LVCMOS_25}
define_io_standard {rst_n_a_i} syn_pad_type {LVCMOS18}
define_io_standard {p2l_clk_p_i} syn_pad_type {DIFF_SSTL_18_Class_II}
define_io_standard {p2l_clk_n_i} syn_pad_type {DIFF_SSTL_18_Class_II}
......@@ -276,8 +263,8 @@ define_io_standard {spec_led_green_o} syn_pad_type {LVCMOS_25}
define_io_standard {spec_led_red_o} syn_pad_type {LVCMOS_25}
define_io_standard {spec_clk_i} syn_pad_type {LVCMOS_25}
define_io_standard {carrier_one_wire_b} syn_pad_type {LVCMOS_25}
define_io_standard {sys_scl_b} syn_pad_type {LVCMOS_25}
define_io_standard {sys_sda_b} syn_pad_type {LVCMOS_25}
define_io_standard {mezz_sys_scl_b} syn_pad_type {LVCMOS_25}
define_io_standard {mezz_sys_sda_b} syn_pad_type {LVCMOS_25}
define_io_standard {mezz_one_wire_b} syn_pad_type {LVCMOS_25}
#
......
hdl/syn/spec/timing_report.twr
View file @ c20e2e0e
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