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FMC TDC 1ns 5cha - Gateware
Commit c2a10e64 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: independent FIFO buffers per channel - top level verified on the SVEC

parent 8b800231
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hdl/rtl/data_formatting.vhd
View file @ c2a10e64
...@@ -137,7 +137,7 @@ architecture rtl of data_formatting is ...@@ -137,7 +137,7 @@ architecture rtl of data_formatting is
signal un_current_retrig_from_roll_over : unsigned(31 downto 0); signal un_current_retrig_from_roll_over : unsigned(31 downto 0);
signal un_acam_fine_time : unsigned(31 downto 0); signal un_acam_fine_time : unsigned(31 downto 0);
signal previous_utc : std_logic_vector(31 downto 0); signal previous_utc : std_logic_vector(31 downto 0);
signal timestamp_valid_int : std_logic;
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
...@@ -149,9 +149,9 @@ begin ...@@ -149,9 +149,9 @@ begin
begin begin
if rising_edge (clk_i) then if rising_edge (clk_i) then
if rst_i = '1' then if rst_i = '1' then
timestamp_valid_o <= '0'; timestamp_valid_int <= '0';
else else
timestamp_valid_o <= acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i; timestamp_valid_int <= acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i;
end if; end if;
end if; end if;
end process; end process;
...@@ -333,8 +333,15 @@ begin ...@@ -333,8 +333,15 @@ begin
full_timestamp(63 downto 32) <= coarse_time; full_timestamp(63 downto 32) <= coarse_time;
full_timestamp(95 downto 64) <= utc; full_timestamp(95 downto 64) <= utc;
full_timestamp(127 downto 96) <= metadata; full_timestamp(127 downto 96) <= metadata;
timestamp_o <= full_timestamp;
process(clk_i)
begin
if rising_edge(clk_i) then
timestamp_o <= full_timestamp;
timestamp_valid_o <= timestamp_valid_int;
end if;
end process;
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_core.vhd
View file @ c2a10e64
...@@ -549,7 +549,7 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD); ...@@ -549,7 +549,7 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
start_dis_o <= '0'; start_dis_o <= '0';
channel_enable_o <= acam_inputs_en(4 downto 0); channel_enable_o <= acam_inputs_en(20 downto 16);
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @ c2a10e64
...@@ -416,9 +416,6 @@ begin ...@@ -416,9 +416,6 @@ begin
end generate gen_fifos; end generate gen_fifos;
irq_tstamp <= '1' when unsigned(irq_channel) /= 0 else '0';
p_gen_1ms_tick : process(clk_tdc_i) p_gen_1ms_tick : process(clk_tdc_i)
begin begin
if rising_edge(clk_tdc_i) then if rising_edge(clk_tdc_i) then
...@@ -515,21 +512,23 @@ begin ...@@ -515,21 +512,23 @@ begin
-- 2 -> ACAM error -- 2 -> ACAM error
cmp_tdc_eic : tdc_eic cmp_tdc_eic : tdc_eic
port map port map
(clk_sys_i => clk_sys_i, (clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i, rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(3 downto 2), wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).dat, wb_dat_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).dat, wb_dat_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).cyc, wb_cyc_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).sel, wb_sel_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).stb, wb_stb_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).we, wb_we_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack, wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall, wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall,
wb_int_o => wb_irq_o, wb_int_o => wb_irq_o,
irq_tdc_tstamps_i => irq_tstamp, irq_tdc_fifo1_i => irq_channel(0),
irq_tdc_time_i => '0', irq_tdc_fifo2_i => irq_channel(1),
irq_tdc_acam_err_i => '0'); irq_tdc_fifo3_i => irq_channel(2),
irq_tdc_fifo4_i => irq_channel(3),
irq_tdc_fifo5_i => irq_channel(4));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals -- Unused wishbone signals
......
hdl/rtl/tdc_core_pkg.vhd
View file @ c2a10e64
...@@ -726,24 +726,25 @@ package tdc_core_pkg is ...@@ -726,24 +726,25 @@ package tdc_core_pkg is
--------------------------------------------------------------------------------------------------- component tdc_eic is
component tdc_eic port (
port rst_n_i : in std_logic;
(rst_n_i : in std_logic; clk_sys_i : in std_logic;
clk_sys_i : in std_logic; wb_adr_i : in std_logic_vector(1 downto 0);
wb_adr_i : in std_logic_vector(1 downto 0); wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0); wb_dat_o : out std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); wb_cyc_i : in std_logic;
wb_cyc_i : in std_logic; wb_sel_i : in std_logic_vector(3 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0); wb_stb_i : in std_logic;
wb_stb_i : in std_logic; wb_we_i : in std_logic;
wb_we_i : in std_logic; wb_ack_o : out std_logic;
wb_ack_o : out std_logic; wb_stall_o : out std_logic;
wb_stall_o : out std_logic; wb_int_o : out std_logic;
wb_int_o : out std_logic; irq_tdc_fifo1_i : in std_logic;
irq_tdc_tstamps_i : in std_logic; irq_tdc_fifo2_i : in std_logic;
irq_tdc_time_i : in std_logic; irq_tdc_fifo3_i : in std_logic;
irq_tdc_acam_err_i : in std_logic); irq_tdc_fifo4_i : in std_logic;
irq_tdc_fifo5_i : in std_logic);
end component tdc_eic; end component tdc_eic;
......
hdl/rtl/tdc_eic.vhd
View file @ c2a10e64
This diff is collapsed.
hdl/rtl/timestamp_fifo.vhd
View file @ c2a10e64
...@@ -85,8 +85,17 @@ architecture rtl of timestamp_fifo is ...@@ -85,8 +85,17 @@ architecture rtl of timestamp_fifo is
signal channel_id : std_logic_vector(2 downto 0); signal channel_id : std_logic_vector(2 downto 0);
signal ts_match : std_logic; signal ts_match : std_logic;
signal seq_counter : unsigned(31 downto 0);
signal timestamp_with_seq : std_logic_vector(127 downto 0);
begin begin
timestamp_with_seq(95 downto 0) <= timestamp_i(95 downto 0); -- TS
timestamp_with_seq(98 downto 96) <= timestamp_i(98 downto 96); -- channel
timestamp_with_seq(100) <= timestamp_i(100); -- slope
timestamp_with_seq(127 downto 101) <= std_logic_vector(seq_counter(26 downto 0));
U_WB_Slave : timestamp_fifo_wb U_WB_Slave : timestamp_fifo_wb
port map ( port map (
rst_n_i => rst_n_sys_i, rst_n_i => rst_n_sys_i,
...@@ -114,6 +123,7 @@ begin ...@@ -114,6 +123,7 @@ begin
if rst_tdc_i = '1' then if rst_tdc_i = '1' then
regs_in.fifo_wr_req_i <= '0'; regs_in.fifo_wr_req_i <= '0';
else else
if(enable_i = '1' and regs_out.fifo_wr_full_o = '0' and ts_match = '1') then if(enable_i = '1' and regs_out.fifo_wr_full_o = '0' and ts_match = '1') then
regs_in.fifo_wr_req_i <= '1'; regs_in.fifo_wr_req_i <= '1';
else else
...@@ -123,24 +133,43 @@ begin ...@@ -123,24 +133,43 @@ begin
end if; end if;
end process; end process;
regs_in.fifo_ts0_i <= timestamp_with_seq(31 downto 0);
regs_in.fifo_ts1_i <= timestamp_with_seq(63 downto 32);
regs_in.fifo_ts2_i <= timestamp_with_seq(95 downto 64);
regs_in.fifo_ts3_i <= timestamp_with_seq(127 downto 96);
p_seq_counter : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' or regs_out.csr_rst_seq_o = '1' then
seq_counter <= (others => '0');
else
if(enable_i = '1' and ts_match = '1') then
seq_counter <= seq_counter + 1;
end if;
end if;
end if;
end process;
p_latch_last_timestamp : process(clk_tdc_i) p_latch_last_timestamp : process(clk_tdc_i)
begin begin
if rising_edge(clk_tdc_i) then if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then if rst_tdc_i = '1' then
regs_in.ltsctl_valid_i <= '0'; regs_in.csr_last_valid_i <= '0';
else else
if (enable_i = '1' and ts_match = '1') then -- latch only the last rising edge TS
regs_in.ltsctl_valid_i <= '1'; if (enable_i = '1' and ts_match = '1' and timestamp_with_seq(100) = '1') then
last_ts <= timestamp_i; regs_in.csr_last_valid_i <= '1';
elsif (regs_out.ltsctl_valid_o = '0' and regs_out.ltsctl_valid_load_o = '1') then last_ts <= timestamp_with_seq;
regs_in.ltsctl_valid_i <= '0'; elsif (regs_out.csr_last_valid_o = '0' and regs_out.csr_last_valid_load_o = '1') then
regs_in.csr_last_valid_i <= '0';
end if; end if;
if (regs_out.ltsctl_valid_o = '0' and regs_out.ltsctl_valid_load_o = '1') then if (regs_out.csr_last_valid_o = '0' and regs_out.csr_last_valid_load_o = '1') then
regs_in.lts0_i <= last_ts(127 downto 96); regs_in.lts0_i <= last_ts(31 downto 0);
regs_in.lts1_i <= last_ts(95 downto 64); regs_in.lts1_i <= last_ts(63 downto 32);
regs_in.lts2_i <= last_ts(63 downto 32); regs_in.lts2_i <= last_ts(95 downto 64);
regs_in.lts3_i <= last_ts(31 downto 0); regs_in.lts3_i <= last_ts(127 downto 96);
end if; end if;
end if; end if;
end if; end if;
...@@ -152,7 +181,7 @@ begin ...@@ -152,7 +181,7 @@ begin
if rst_tdc_i = '1' or enable_i = '0' then if rst_tdc_i = '1' or enable_i = '0' then
buf_irq_int <= '0'; buf_irq_int <= '0';
else else
if(buf_count = 0) then if(regs_out.fifo_wr_empty_o = '1') then
buf_irq_int <= '0'; buf_irq_int <= '0';
tmr_timeout <= (others => '0'); tmr_timeout <= (others => '0');
else else
...@@ -172,7 +201,7 @@ begin ...@@ -172,7 +201,7 @@ begin
-- Case 2: amount of data exceeded the threshold - assert the IRQ -- Case 2: amount of data exceeded the threshold - assert the IRQ
-- line immediately. -- line immediately.
if(buf_count > unsigned(irq_threshold_i(9 downto 0))) then if(regs_out.fifo_wr_full_o = '1' or (buf_count > unsigned(irq_threshold_i(9 downto 0)))) then
buf_irq_int <= '1'; buf_irq_int <= '1';
end if; end if;
end if; end if;
......
hdl/rtl/timestamp_fifo_wb.vhd
View file @ c2a10e64
This diff is collapsed.
hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
View file @ c2a10e64
...@@ -2,11 +2,11 @@ ...@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for Timestamp FIFO -- Title : Wishbone slave core for Timestamp FIFO
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd -- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from timestamp_fifo_wb.wb -- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Tue Apr 14 16:47:08 2015 -- Created : Mon Apr 20 17:34:12 2015
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timestamp_fifo_wb.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -22,22 +22,28 @@ package tsf_wbgen2_pkg is ...@@ -22,22 +22,28 @@ package tsf_wbgen2_pkg is
type t_tsf_in_registers is record type t_tsf_in_registers is record
fifo_wr_req_i : std_logic; fifo_wr_req_i : std_logic;
fifo_value_i : std_logic_vector(127 downto 0); fifo_ts0_i : std_logic_vector(31 downto 0);
fifo_ts1_i : std_logic_vector(31 downto 0);
fifo_ts2_i : std_logic_vector(31 downto 0);
fifo_ts3_i : std_logic_vector(31 downto 0);
lts0_i : std_logic_vector(31 downto 0); lts0_i : std_logic_vector(31 downto 0);
lts1_i : std_logic_vector(31 downto 0); lts1_i : std_logic_vector(31 downto 0);
lts2_i : std_logic_vector(31 downto 0); lts2_i : std_logic_vector(31 downto 0);
lts3_i : std_logic_vector(31 downto 0); lts3_i : std_logic_vector(31 downto 0);
ltsctl_valid_i : std_logic; csr_last_valid_i : std_logic;
end record; end record;
constant c_tsf_in_registers_init_value: t_tsf_in_registers := ( constant c_tsf_in_registers_init_value: t_tsf_in_registers := (
fifo_wr_req_i => '0', fifo_wr_req_i => '0',
fifo_value_i => (others => '0'), fifo_ts0_i => (others => '0'),
fifo_ts1_i => (others => '0'),
fifo_ts2_i => (others => '0'),
fifo_ts3_i => (others => '0'),
lts0_i => (others => '0'), lts0_i => (others => '0'),
lts1_i => (others => '0'), lts1_i => (others => '0'),
lts2_i => (others => '0'), lts2_i => (others => '0'),
lts3_i => (others => '0'), lts3_i => (others => '0'),
ltsctl_valid_i => '0' csr_last_valid_i => '0'
); );
-- Output registers (WB slave -> user design) -- Output registers (WB slave -> user design)
...@@ -46,16 +52,18 @@ package tsf_wbgen2_pkg is ...@@ -46,16 +52,18 @@ package tsf_wbgen2_pkg is
fifo_wr_full_o : std_logic; fifo_wr_full_o : std_logic;
fifo_wr_empty_o : std_logic; fifo_wr_empty_o : std_logic;
fifo_wr_usedw_o : std_logic_vector(9 downto 0); fifo_wr_usedw_o : std_logic_vector(9 downto 0);
ltsctl_valid_o : std_logic; csr_last_valid_o : std_logic;
ltsctl_valid_load_o : std_logic; csr_last_valid_load_o : std_logic;
csr_rst_seq_o : std_logic;
end record; end record;
constant c_tsf_out_registers_init_value: t_tsf_out_registers := ( constant c_tsf_out_registers_init_value: t_tsf_out_registers := (
fifo_wr_full_o => '0', fifo_wr_full_o => '0',
fifo_wr_empty_o => '0', fifo_wr_empty_o => '0',
fifo_wr_usedw_o => (others => '0'), fifo_wr_usedw_o => (others => '0'),
ltsctl_valid_o => '0', csr_last_valid_o => '0',
ltsctl_valid_load_o => '0' csr_last_valid_load_o => '0',
csr_rst_seq_o => '0'
); );
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers; function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
function f_x_to_zero (x:std_logic) return std_logic; function f_x_to_zero (x:std_logic) return std_logic;
...@@ -87,12 +95,15 @@ function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers is ...@@ -87,12 +95,15 @@ function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers is
variable tmp: t_tsf_in_registers; variable tmp: t_tsf_in_registers;
begin begin
tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i); tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i);
tmp.fifo_value_i := f_x_to_zero(left.fifo_value_i) or f_x_to_zero(right.fifo_value_i); tmp.fifo_ts0_i := f_x_to_zero(left.fifo_ts0_i) or f_x_to_zero(right.fifo_ts0_i);
tmp.fifo_ts1_i := f_x_to_zero(left.fifo_ts1_i) or f_x_to_zero(right.fifo_ts1_i);
tmp.fifo_ts2_i := f_x_to_zero(left.fifo_ts2_i) or f_x_to_zero(right.fifo_ts2_i);
tmp.fifo_ts3_i := f_x_to_zero(left.fifo_ts3_i) or f_x_to_zero(right.fifo_ts3_i);
tmp.lts0_i := f_x_to_zero(left.lts0_i) or f_x_to_zero(right.lts0_i); tmp.lts0_i := f_x_to_zero(left.lts0_i) or f_x_to_zero(right.lts0_i);
tmp.lts1_i := f_x_to_zero(left.lts1_i) or f_x_to_zero(right.lts1_i); tmp.lts1_i := f_x_to_zero(left.lts1_i) or f_x_to_zero(right.lts1_i);
tmp.lts2_i := f_x_to_zero(left.lts2_i) or f_x_to_zero(right.lts2_i); tmp.lts2_i := f_x_to_zero(left.lts2_i) or f_x_to_zero(right.lts2_i);
tmp.lts3_i := f_x_to_zero(left.lts3_i) or f_x_to_zero(right.lts3_i); tmp.lts3_i := f_x_to_zero(left.lts3_i) or f_x_to_zero(right.lts3_i);
tmp.ltsctl_valid_i := f_x_to_zero(left.ltsctl_valid_i) or f_x_to_zero(right.ltsctl_valid_i); tmp.csr_last_valid_i := f_x_to_zero(left.csr_last_valid_i) or f_x_to_zero(right.csr_last_valid_i);
return tmp; return tmp;
end function; end function;
end package body; end package body;
hdl/rtl/wbgen/tdc_eic.wb
View file @ c2a10e64
...@@ -5,25 +5,41 @@ peripheral { ...@@ -5,25 +5,41 @@ peripheral {
prefix = "tdc_eic"; prefix = "tdc_eic";
irq {
name = "FMC TDC timestamps interrupt (FIFO1)";
description = "FMC TDC FIFO1 not empty.";
prefix = "tdc_fifo1";
trigger = LEVEL_1;
};
irq {
name = "FMC TDC timestamps interrupt (FIFO2)";
description = "FMC TDC FIFO1 not empty.";
prefix = "tdc_fifo2";
trigger = LEVEL_1;
};
irq { irq {
name = "FMC TDC timestamps interrupt"; name = "FMC TDC timestamps interrupt (FIFO3)";
description = "FMC TDC timestamp interrupt (rising edge sensitive)."; description = "FMC TDC FIFO3 not empty.";
prefix = "tdc_tstamps"; prefix = "tdc_fifo3";
trigger = EDGE_RISING; trigger = LEVEL_1;
}; };
irq { irq {
name = "FMC TDC time interrupt"; name = "FMC TDC timestamps interrupt (FIFO4)";
description = "FMC TDC time interrupt (rising edge sensitive)."; description = "FMC TDC FIFO4 not empty.";
prefix = "tdc_time"; prefix = "tdc_fifo4";
trigger = EDGE_RISING; trigger = LEVEL_1;
}; };
irq { irq {
name = "FMC TDC acam error interrupt"; name = "FMC TDC timestamps interrupt (FIFO5)";
description = "FMC slot 1 acam error interrupt (rising edge sensitive)."; description = "FMC TDC FIFO5 not empty.";
prefix = "tdc_acam_err"; prefix = "tdc_fifo5";
trigger = EDGE_RISING; trigger = LEVEL_1;
}; };
}; };
hdl/rtl/timestamp_fifo_wb.wb → hdl/rtl/wbgen/timestamp_fifo_wb.wb
View file @ c2a10e64
...@@ -15,14 +15,35 @@ peripheral { ...@@ -15,14 +15,35 @@ peripheral {
name = "Timestamp FIFO"; name = "Timestamp FIFO";
clock = "clk_tdc_i"; clock = "clk_tdc_i";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT, FIFO_CLEAR};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
field { field {
name = "The timestamp"; name = "The timestamp (word 0)";
prefix = "value"; prefix = "ts0";
type = SLV; type = SLV;
size = 128; size = 32;
};
field {
name = "The timestamp (word 1)";
prefix = "ts1";
type = SLV;
size = 32;
};
field {
name = "The timestamp (word 2)";
prefix = "ts2";
type = SLV;
size = 32;
};
field {
name = "The timestamp (word 4)";
prefix = "ts3";
type = SLV;
size = 32;
}; };
}; };
...@@ -84,19 +105,31 @@ peripheral { ...@@ -84,19 +105,31 @@ peripheral {
}; };
}; };
reg { reg {
name = "Last Timestamp Control/Status"; name = "Control/Status";
prefix = "LTSCTL"; prefix = "CSR";
field { field {
name = "Last Timestamp Valid"; name = "Last Timestamp Valid";
clock = "clk_tdc_i"; clock = "clk_tdc_i";
prefix = "VALID"; prefix = "LAST_VALID";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
load = LOAD_EXT; load = LOAD_EXT;
}; };
field {
name = "Reset Sequence Counter";
clock = "clk_tdc_i";
prefix = "RST_SEQ";
type = MONOSTABLE;
};
}; };
}; };
hdl/syn/svec/wr_svec_tdc.xise
View file @ c2a10e64
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hdl/testbench/svec/main.sv
View file @ c2a10e64
...@@ -51,12 +51,12 @@ module fake_acam( ...@@ -51,12 +51,12 @@ module fake_acam(
if (addr == 8) begin if (addr == 8) begin
acam_fifo_entry ent; acam_fifo_entry ent;
ent=fifo1.pop_front(); ent=fifo1.pop_front();
data <= ent.ts | (ent.channel << 26); data <= ent.ts | (ent.channel << 26) | (1<<17);
end else if (addr == 9) begin end else if (addr == 9) begin
acam_fifo_entry ent; acam_fifo_entry ent;
ent=fifo2.pop_front(); ent=fifo2.pop_front();
data <= ent.ts | (ent.channel << 26); data <= ent.ts | (ent.channel << 26) | (1<<17);
end else end else
data <= 28'bz; data <= 28'bz;
...@@ -218,7 +218,7 @@ module main; ...@@ -218,7 +218,7 @@ module main;
acc.write('hc13004, 'hf); // enable EIC irq acc.write('hc13004, 'hf); // enable EIC irq
acc.write('hc12084, 'h1f); // enable all ACAM inputs acc.write('hc12084, 'h1f0000); // enable all ACAM inputs
acc.write('hc120fc, (1<<0)); // start acquisition acc.write('hc120fc, (1<<0)); // start acquisition
acc.write('hc120fc, (1<<0)); // start acquisition acc.write('hc120fc, (1<<0)); // start acquisition
...@@ -230,11 +230,11 @@ module main; ...@@ -230,11 +230,11 @@ module main;
#300us; #300us;
fork fork
forever begin forever begin
acc.read('hc15000 + `ADDR_TSF_LTSCTL, d); acc.read('hc15000 + `ADDR_TSF_CSR, d);
if(d&1) begin if(d&1) begin
uint64_t t0,t1,t2,t3; uint64_t t0,t1,t2,t3;
acc.write('hc15000 + `ADDR_TSF_LTSCTL, 0); acc.write('hc15000 + `ADDR_TSF_CSR, 0);
acc.read('hc15000 + `ADDR_TSF_LTS0, t0); acc.read('hc15000 + `ADDR_TSF_LTS0, t0);
acc.read('hc15000 + `ADDR_TSF_LTS1, t1); acc.read('hc15000 + `ADDR_TSF_LTS1, t1);
acc.read('hc15000 + `ADDR_TSF_LTS2, t2); acc.read('hc15000 + `ADDR_TSF_LTS2, t2);
...@@ -244,8 +244,23 @@ module main; ...@@ -244,8 +244,23 @@ module main;
end end
acc.read('hc15000 + `ADDR_TSF_FIFO_CSR, d);
// $display("FIFO CSR %x", d);
/* -----\/----- EXCLUDED -----\/-----
if(!(d&`TSF_FIFO_CSR_EMPTY)) begin
uint64_t t0,t1,t2,t3;
acc.read('hc15000 + `ADDR_TSF_FIFO_R0, t0);
acc.read('hc15000 + `ADDR_TSF_FIFO_R1, t1);
acc.read('hc15000 + `ADDR_TSF_FIFO_R2, t2);
acc.read('hc15000 + `ADDR_TSF_FIFO_R3, t3);
$display("Fifo: %08x %08x %08x %08x",t0,t1,t2,t3);
end
-----/\----- EXCLUDED -----/\----- */
end end
......
hdl/testbench/svec/wave.do
View file @ c2a10e64
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