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FMC TDC 1ns 5cha - Gateware
Commit c64cb20c authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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rtl/acam_databus_interface: make design fully synchronous, extend read cycle… 

rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing
parent 2b303836
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Showing with 45 additions and 23 deletions
hdl/rtl/acam_databus_interface.vhd
View file @ c64cb20c
...@@ -81,6 +81,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions ...@@ -81,6 +81,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library -- Specific library
library work; library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.gencores_pkg.all;
--================================================================================================= --=================================================================================================
...@@ -135,13 +136,13 @@ end acam_databus_interface; ...@@ -135,13 +136,13 @@ end acam_databus_interface;
architecture rtl of acam_databus_interface is architecture rtl of acam_databus_interface is
type t_acam_interface is (IDLE, RD_START, RD_FETCH, RD_ACK, WR_START, WR_PUSH, WR_ACK); type t_acam_interface is (IDLE, RD_START, RD_FETCH, RD_FETCH2, RD_FETCH3, RD_ACK, WR_START, WR_PUSH, WR_ACK);
signal acam_data_st, nxt_acam_data_st : t_acam_interface; signal acam_data_st, nxt_acam_data_st : t_acam_interface;
signal ef1_synch, ef2_synch : std_logic_vector(1 downto 0) := (others =>'1'); signal ef1_synch, ef2_synch : std_logic;
signal ack, rd, rd_extend : std_logic; signal ack, rd, rd_extend : std_logic;
signal wr, wr_extend, wr_remove : std_logic; signal wr, wr_extend, wr_remove : std_logic;
signal rst_n : std_logic;
--================================================================================================= --=================================================================================================
...@@ -153,19 +154,22 @@ begin ...@@ -153,19 +154,22 @@ begin
-- Input Synchronizers -- -- Input Synchronizers --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
input_registers: process (clk_i) rst_n <= not rst_n;
begin
if rising_edge (clk_i) then cmp_sync_ef1: gc_sync_ffs
if rst_i ='1' then port map (
ef1_synch <= (others =>'1'); clk_i => clk_i,
ef2_synch <= (others =>'1'); rst_n_i => rst_n,
else data_i => ef1_i,
ef1_synch <= ef1_i & ef1_synch(1); synced_o => ef1_synch);
ef2_synch <= ef2_i & ef2_synch(1);
end if; cmp_sync_ef2: gc_sync_ffs
end if; port map (
end process; clk_i => clk_i,
rst_n_i => rst_n,
data_i => ef2_i,
synced_o => ef2_synch);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- FSM -- -- FSM --
...@@ -224,6 +228,28 @@ begin ...@@ -224,6 +228,28 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when RD_FETCH => when RD_FETCH =>
-----------------------------------------------
ack <= '0';
rd_extend <= '1';
wr_extend <= '0';
wr_remove <= '0';
-----------------------------------------------
nxt_acam_data_st <= RD_FETCH2;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when RD_FETCH2 =>
-----------------------------------------------
ack <= '0';
rd_extend <= '1';
wr_extend <= '0';
wr_remove <= '0';
-----------------------------------------------
nxt_acam_data_st <= RD_FETCH3;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when RD_FETCH3 =>
----------------------------------------------- -----------------------------------------------
ack <= '0'; ack <= '0';
rd_extend <= '1'; rd_extend <= '1';
...@@ -298,7 +324,7 @@ begin ...@@ -298,7 +324,7 @@ begin
ack_o <= ack; ack_o <= ack;
-- to the 28 bits databus output we add the ef flags to arrive to a 32 bits word -- to the 28 bits databus output we add the ef flags to arrive to a 32 bits word
dat_o <= ef1_synch(0) & ef2_synch(0) & "00" & data_bus_io; dat_o <= ef1_synch & ef2_synch & "00" & data_bus_io;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -332,12 +358,8 @@ output_registers: process (clk_i) ...@@ -332,12 +358,8 @@ output_registers: process (clk_i)
-- EF to the data_engine -- -- EF to the data_engine --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
ef1_o <= ef1_synch(0); -- ef1 after two synchronization registers ef1_o <= ef1_synch; -- ef1 after two synchronization registers
ef1_meta_o <= ef1_synch(1); -- ef1 after one synchronization register ef2_o <= ef2_synch; -- ef1 after two synchronization registers
ef2_o <= ef2_synch(0); -- ef1 after two synchronization registers
ef2_meta_o <= ef2_synch(1); -- ef1 after one synchronization register
end rtl; end rtl;
--================================================================================================= --=================================================================================================
......
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