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FMC TDC 1ns 5cha - Gateware
Commit c863a036 authored by egousiou's avatar egousiou
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small change on svec top_tdc: irq synchronisation 

git-svn-id: http://svn.ohwr.org/fmc-tdc@137 85dfdc96-de2c-444c-878d-45b388be74a9
parent 0b9d3454
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hdl/syn/svec/svec-tdc-fmc.gise
View file @ c863a036
...@@ -103,7 +103,7 @@ ...@@ -103,7 +103,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1383763118" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1383762954"> <transform xil_pn:end_ts="1383822997" xil_pn:in_ck="5268971704634117961" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="7543648610729664005" xil_pn:start_ts="1383822823">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -125,7 +125,7 @@ ...@@ -125,7 +125,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1383763130" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1383763118"> <transform xil_pn:end_ts="1383823013" xil_pn:in_ck="-3760130385703199631" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="8504525175841796663" xil_pn:start_ts="1383822997">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -135,7 +135,7 @@ ...@@ -135,7 +135,7 @@
<outfile xil_pn:name="top_tdc.ngd"/> <outfile xil_pn:name="top_tdc.ngd"/>
<outfile xil_pn:name="top_tdc_ngdbuild.xrpt"/> <outfile xil_pn:name="top_tdc_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1383763330" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1383763130"> <transform xil_pn:end_ts="1383823223" xil_pn:in_ck="-7440346353620165565" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="7568465460566446564" xil_pn:start_ts="1383823013">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
...@@ -148,7 +148,7 @@ ...@@ -148,7 +148,7 @@
<outfile xil_pn:name="top_tdc_summary.xml"/> <outfile xil_pn:name="top_tdc_summary.xml"/>
<outfile xil_pn:name="top_tdc_usage.xml"/> <outfile xil_pn:name="top_tdc_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1383763581" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1383763330"> <transform xil_pn:end_ts="1383823767" xil_pn:in_ck="4998236143670007004" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-7978487711023391987" xil_pn:start_ts="1383823223">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -163,7 +163,7 @@ ...@@ -163,7 +163,7 @@
<outfile xil_pn:name="top_tdc_pad.txt"/> <outfile xil_pn:name="top_tdc_pad.txt"/>
<outfile xil_pn:name="top_tdc_par.xrpt"/> <outfile xil_pn:name="top_tdc_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1383763691" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1383763630"> <transform xil_pn:end_ts="1383823828" xil_pn:in_ck="182976557419624816" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="-5293564962942599218" xil_pn:start_ts="1383823767">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
...@@ -175,7 +175,7 @@ ...@@ -175,7 +175,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1383763581" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1383763560"> <transform xil_pn:end_ts="1383823767" xil_pn:in_ck="-7440346353620165697" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1383823744">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/syn/svec/svec-tdc-fmc.xise
View file @ c863a036
...@@ -418,7 +418,7 @@ ...@@ -418,7 +418,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="58"/> <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file> </file>
<file xil_pn:name="../../top/svec/top_tdc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../top/svec/top_tdc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/> <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file> </file>
<file xil_pn:name="../../ip_cores/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
...@@ -446,7 +446,7 @@ ...@@ -446,7 +446,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/> <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file> </file>
<file xil_pn:name="../../ip_cores/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
...@@ -462,7 +462,7 @@ ...@@ -462,7 +462,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../ip_cores/common/gc_reset.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
......
hdl/syn/svec/top_tdc.bin
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hdl/syn/svec/top_tdc.twr
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hdl/syn/svec/top_tdc_summary.html
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hdl/top/svec/top_tdc.vhd
View file @ c863a036
...@@ -385,8 +385,8 @@ architecture rtl of top_tdc is ...@@ -385,8 +385,8 @@ architecture rtl of top_tdc is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Interrupts -- Interrupts
signal irq_to_vmecore : std_logic; signal irq_to_vmecore : std_logic;
signal tdc1_irq, tdc1_irq_synch : std_logic; signal tdc1_irq, tdc2_irq : std_logic;
signal tdc2_irq, tdc2_irq_synch : std_logic; signal tdc1_irq_synch, tdc2_irq_synch : std_logic_vector (1 downto 0);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Carrier other signals -- Carrier other signals
...@@ -802,30 +802,26 @@ begin ...@@ -802,30 +802,26 @@ begin
rst_n_i => rst_n_sys, rst_n_i => rst_n_sys,
slave_i => cnx_master_out(c_SLAVE_VIC), slave_i => cnx_master_out(c_SLAVE_VIC),
slave_o => cnx_master_in(c_SLAVE_VIC), slave_o => cnx_master_in(c_SLAVE_VIC),
irqs_i(0) => tdc1_irq_synch, irqs_i(0) => tdc1_irq_synch(1),
irqs_i(1) => tdc2_irq_synch, irqs_i(1) => tdc2_irq_synch(1),
irq_master_o => irq_to_vmecore); irq_master_o => irq_to_vmecore);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- since the TDC cores work in their PLL clock domains (tdc1_clk_125m and tdc2_clk_125m) -- since the TDC cores work in their PLL clock domains (tdc1_clk_125m and tdc2_clk_125m)
-- and the rest works with the system clock (clk_62m5_sys) we need to synchronize -- and the rest works with the system clock (clk_62m5_sys) interrupt pulses need to be
-- interrupt pulses. -- synchronized
cmp_sync_irq0 : gc_pulse_synchronizer irq_pulse_synchronizer: process (clk_62m5_sys)
port map begin
(clk_in_i => tdc1_clk_125m, if rising_edge (clk_62m5_sys) then
clk_out_i => clk_62m5_sys, if rst_n_sys = '0' then
rst_n_i => rst_n_sys, tdc1_irq_synch <= (others => '0');
d_p_i => tdc1_irq, tdc2_irq_synch <= (others => '0');
q_p_o => tdc1_irq_synch); else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- tdc1_irq_synch <= tdc1_irq_synch(0) & tdc1_irq;
cmp_sync_irq1 : gc_pulse_synchronizer tdc2_irq_synch <= tdc2_irq_synch(0) & tdc2_irq;
port map end if;
(clk_in_i => tdc1_clk_125m, end if;
clk_out_i => clk_62m5_sys, end process;
rst_n_i => rst_n_sys,
d_p_i => tdc2_irq,
q_p_o => tdc2_irq_synch);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
......
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