Commit cb30b5d1 authored by penacoba's avatar penacoba

cleaned up version of the PLL test synthesis results


git-svn-id: http://svn.ohwr.org/fmc-tdc@35 85dfdc96-de2c-444c-878d-45b388be74a9
parent b5ae1362
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
</messages>
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/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syn_tdc.edf 1310751057
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syn_tdc.edf 1310975041
OK
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Release 13.1 - par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Fri Jul 15 19:32:01 2011
Mon Jul 18 09:44:59 2011
# NOTE: This file is designed to be imported into a spreadsheet program
......@@ -190,7 +190,7 @@ F14||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
F15||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
F16||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
F17||IOBS|IO_L51N_0|UNUSED||0|||||||||
F18|spec_aux4_o|IOB|IO_L1P_A25_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|NO|NONE|
F18|spec_aux4_o|IOB|IO_L1P_A25_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|YES|NONE|
F19||IOBS|IO_L1N_A24_VREF_1|UNUSED||1|||||||||
F20|spec_aux3_o|IOB|IO_L29N_A22_M1A14_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|NO|NONE|
F21|p2l_data_i(14)|IOB|IO_L31P_A19_M1CKE_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE|
......@@ -213,7 +213,7 @@ G15||IOBS|IO_L49N_0|UNUSED||0|||||||||
G16||IOBM|IO_L51P_0|UNUSED||0|||||||||
G17|||TDO||||||||||||
G18|||GND||||||||||||
G19|spec_aux2_o|IOB|IO_L29P_A23_M1A13_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|YES|NONE|
G19|spec_aux2_o|IOB|IO_L29P_A23_M1A13_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|NO|NONE|
G20|p2l_data_i(6)|IOB|IO_L35P_A11_M1A7_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE|
G21|||VCCO_1|||1|||||1.80||||
G22|p2l_data_i(5)|IOB|IO_L35N_A10_M1A2_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE|
......
Release 13.1 par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
lxplus427.cern.ch:: Fri Jul 15 19:31:40 2011
lxplus427.cern.ch:: Mon Jul 18 09:44:37 2011
par -ol high syn_tdc.ncd par_tdc
......@@ -27,11 +27,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 177 out of 27,288 1%
Number used as logic: 176 out of 27,288 1%
Number using O6 output only: 108
Number using O5 output only: 30
Number using O5 and O6: 38
Number of Slice LUTs: 193 out of 27,288 1%
Number used as logic: 192 out of 27,288 1%
Number using O6 output only: 121
Number using O5 output only: 31
Number using O5 and O6: 40
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 1
......@@ -40,11 +40,11 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 63 out of 6,822 1%
Number of LUT Flip Flop pairs used: 179
Number with an unused Flip Flop: 93 out of 179 51%
Number with an unused LUT: 2 out of 179 1%
Number of fully used LUT-FF pairs: 84 out of 179 46%
Number of occupied Slices: 80 out of 6,822 1%
Number of LUT Flip Flop pairs used: 195
Number with an unused Flip Flop: 109 out of 195 55%
Number with an unused LUT: 2 out of 195 1%
Number of fully used LUT-FF pairs: 84 out of 195 43%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -166,29 +166,29 @@ WARNING:Par:288 - The signal int_flag_i_IBUF has no load. PAR will not attempt
Starting Router
Phase 1 : 1007 unrouted; REAL time: 7 secs
Phase 1 : 1136 unrouted; REAL time: 7 secs
Phase 2 : 716 unrouted; REAL time: 9 secs
Phase 2 : 827 unrouted; REAL time: 9 secs
Phase 3 : 149 unrouted; REAL time: 10 secs
Phase 3 : 180 unrouted; REAL time: 10 secs
Phase 4 : 150 unrouted; (Setup:19402, Hold:0, Component Switching Limit:0) REAL time: 12 secs
Phase 4 : 181 unrouted; (Setup:24717, Hold:0, Component Switching Limit:0) REAL time: 12 secs
Updating file: par_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:20177, Hold:0, Component Switching Limit:0) REAL time: 13 secs
Phase 5 : 0 unrouted; (Setup:27847, Hold:0, Component Switching Limit:0) REAL time: 12 secs
Phase 6 : 0 unrouted; (Setup:20151, Hold:0, Component Switching Limit:0) REAL time: 17 secs
Phase 6 : 0 unrouted; (Setup:27646, Hold:0, Component Switching Limit:0) REAL time: 17 secs
Updating file: par_tdc.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:20151, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 7 : 0 unrouted; (Setup:27646, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 8 : 0 unrouted; (Setup:20151, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 8 : 0 unrouted; (Setup:27646, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 9 : 0 unrouted; (Setup:20151, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 9 : 0 unrouted; (Setup:27646, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 10 : 0 unrouted; (Setup:17366, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 10 : 0 unrouted; (Setup:19904, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Total REAL time to Router completion: 20 secs
Total CPU time to Router completion: 20 secs
......@@ -208,9 +208,9 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| spec_clk | BUFGMUX_X2Y3| No | 26 | 0.659 | 2.387 |
| spec_clk | BUFGMUX_X2Y3| No | 42 | 0.669 | 2.387 |
+---------------------+--------------+------+------+------------+-------------+
| clk | BUFGMUX_X3Y7| No | 13 | 0.667 | 2.382 |
| clk | BUFGMUX_X3Y7| No | 13 | 0.659 | 2.382 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -218,7 +218,7 @@ only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 17366 (Setup: 17366, Hold: 0, Component Switching Limit: 0)
Timing Score: 19904 (Setup: 19904, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
......@@ -249,15 +249,15 @@ Asterisk (*) preceding a constraint indicates it was not met.
P "spec_aux0_i" TO TIMEGRP "clk" 6 | HOLD | 6.080ns| | 0| 0
ns | | | | |
----------------------------------------------------------------------------------------------------------
* TS_spec_clk_i = PERIOD TIMEGRP "spec_clk_ | SETUP | -2.369ns| 7.369ns| 8| 11437
i" 5 ns HIGH 50% | HOLD | 0.437ns| | 0| 0
* TS_spec_clk_i = PERIOD TIMEGRP "spec_clk_ | SETUP | -2.332ns| 7.332ns| 17| 13975
i" 5 ns HIGH 50% | HOLD | 0.429ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc_led_status_o_clk = MAXDELAY FROM T | MAXDELAY | 2.191ns| 3.809ns| 0| 0
IMEGRP "clk" TO TIMEGRP "tdc_led_ | | | | |
status_o" 6 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 5 | SETUP | 3.272ns| 4.728ns| 0| 0
0% | HOLD | 0.497ns| | 0| 0
TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 5 | SETUP | 3.102ns| 4.898ns| 0| 0
0% | HOLD | 0.463ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_spec_led_green_o_spec_clk = MAXDELAY F | MAXDELAY | 44.140ns| 3.860ns| 0| 0
ROM TIMEGRP "spec_clk" TO TIMEGRP | | | | |
......@@ -277,14 +277,14 @@ All signals are completely routed.
WARNING:Par:283 - There are 68 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 22 secs
Total REAL time to PAR completion: 21 secs
Total CPU time to PAR completion: 21 secs
Peak Memory Usage: 504 MB
Peak Memory Usage: 511 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 9 errors found.
Timing: Completed - 18 errors found.
Number of error messages: 0
Number of warning messages: 71
......
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_aux0_i_clk = MAXDELAY FROM TIMEGRP &quot;spec_aux0_i&quot; TO TIMEGRP &quot;clk&quot; 6 ns</twConstName><twConstData type="SETUP" slack="-5.929" best="11.929" units="ns" errors="1" score="5929"/><twConstData type="HOLD" slack="6.080" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk_i = PERIOD TIMEGRP &quot;spec_clk_i&quot; 5 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="-2.369" best="7.369" units="ns" errors="8" score="11437"/><twConstData type="HOLD" slack="0.437" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_tdc_led_status_o_clk = MAXDELAY FROM TIMEGRP &quot;clk&quot; TO TIMEGRP &quot;tdc_led_status_o&quot; 6 ns</twConstName><twConstData type="MAXDELAY" slack="2.191" best="3.809" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_clk = PERIOD TIMEGRP &quot;clk&quot; 8 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="3.272" best="4.728" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.497" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_led_green_o_spec_clk = MAXDELAY FROM TIMEGRP &quot;spec_clk&quot; TO TIMEGRP &quot;spec_led_green_o&quot; 48 ns</twConstName><twConstData type="MAXDELAY" slack="44.140" best="3.860" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk = PERIOD TIMEGRP &quot;spec_clk&quot; 50 ns HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="46.430" best="3.570" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">2</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_aux0_i_clk = MAXDELAY FROM TIMEGRP &quot;spec_aux0_i&quot; TO TIMEGRP &quot;clk&quot; 6 ns</twConstName><twConstData type="SETUP" slack="-5.929" best="11.929" units="ns" errors="1" score="5929"/><twConstData type="HOLD" slack="6.080" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk_i = PERIOD TIMEGRP &quot;spec_clk_i&quot; 5 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="-2.332" best="7.332" units="ns" errors="17" score="13975"/><twConstData type="HOLD" slack="0.429" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_tdc_led_status_o_clk = MAXDELAY FROM TIMEGRP &quot;clk&quot; TO TIMEGRP &quot;tdc_led_status_o&quot; 6 ns</twConstName><twConstData type="MAXDELAY" slack="2.191" best="3.809" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_clk = PERIOD TIMEGRP &quot;clk&quot; 8 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="3.102" best="4.898" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.463" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_led_green_o_spec_clk = MAXDELAY FROM TIMEGRP &quot;spec_clk&quot; TO TIMEGRP &quot;spec_led_green_o&quot; 48 ns</twConstName><twConstData type="MAXDELAY" slack="44.140" best="3.860" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk = PERIOD TIMEGRP &quot;spec_clk&quot; 50 ns HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="46.430" best="3.570" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">2</twUnmetConstCnt></twSumRpt></twBody></twReport>
......@@ -36,15 +36,15 @@ Asterisk (*) preceding a constraint indicates it was not met.
P "spec_aux0_i" TO TIMEGRP "clk" 6 | HOLD | 6.080ns| | 0| 0
ns | | | | |
----------------------------------------------------------------------------------------------------------
* TS_spec_clk_i = PERIOD TIMEGRP "spec_clk_ | SETUP | -2.369ns| 7.369ns| 8| 11437
i" 5 ns HIGH 50% | HOLD | 0.437ns| | 0| 0
* TS_spec_clk_i = PERIOD TIMEGRP "spec_clk_ | SETUP | -2.332ns| 7.332ns| 17| 13975
i" 5 ns HIGH 50% | HOLD | 0.429ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc_led_status_o_clk = MAXDELAY FROM T | MAXDELAY | 2.191ns| 3.809ns| 0| 0
IMEGRP "clk" TO TIMEGRP "tdc_led_ | | | | |
status_o" 6 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 5 | SETUP | 3.272ns| 4.728ns| 0| 0
0% | HOLD | 0.497ns| | 0| 0
TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 5 | SETUP | 3.102ns| 4.898ns| 0| 0
0% | HOLD | 0.463ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_spec_led_green_o_spec_clk = MAXDELAY F | MAXDELAY | 44.140ns| 3.860ns| 0| 0
ROM TIMEGRP "spec_clk" TO TIMEGRP | | | | |
......@@ -53,14 +53,14 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_spec_clk = PERIOD TIMEGRP "spec_clk" 5 | MINPERIOD | 46.430ns| 3.570ns| 0| 0
0 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Unconstrained OFFSET IN BEFORE analysis f | SETUP | N/A| 20.944ns| N/A| 0
Unconstrained OFFSET IN BEFORE analysis f | SETUP | N/A| 13.053ns| N/A| 0
or clock "spec_clk" | | | | |
----------------------------------------------------------------------------------------------------------
Unconstrained OFFSET OUT AFTER analysis f | MAXDELAY | N/A| 17.070ns| N/A| 0
Unconstrained OFFSET OUT AFTER analysis f | MAXDELAY | N/A| 19.174ns| N/A| 0
or clock "spec_clk" | | | | |
----------------------------------------------------------------------------------------------------------
Unconstrained path analysis | MAXDELAY | N/A| 17.050ns| N/A| 0
| HOLD | 1.402ns| | 0| 0
| HOLD | 2.135ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -80,9 +80,9 @@ Setup/Hold to clock spec_clk_i
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
rst_n_a_i | 20.944(R)| SLOW | -0.113(R)| SLOW |spec_clk | 0.000|
rst_n_a_i | 13.053(R)| SLOW | -1.570(R)| SLOW |spec_clk | 0.000|
spec_aux0_i | 8.165(R)| SLOW | -4.426(R)| FAST |spec_clk | 0.000|
spec_aux1_i | 18.568(R)| SLOW | -2.071(R)| FAST |spec_clk | 0.000|
spec_aux1_i | 9.761(R)| SLOW | -1.373(R)| SLOW |spec_clk | 0.000|
------------+------------+------------+------------+------------+------------------+--------+
Setup/Hold to clock tdc_clk_n_i
......@@ -106,12 +106,12 @@ Clock spec_clk_i to Pad
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
---------------+-----------------+------------+-----------------+------------+------------------+--------+
pll_cs_o | 14.728(R)| SLOW | 6.361(R)| FAST |spec_clk | 0.000|
pll_cs_o | 14.889(R)| SLOW | 6.586(R)| FAST |spec_clk | 0.000|
pll_sclk_o | 8.380(R)| SLOW | 3.127(R)| FAST |spec_clk | 0.000|
pll_sdi_o | 17.070(R)| SLOW | 6.277(R)| FAST |spec_clk | 0.000|
spec_aux2_o | 8.249(R)| SLOW | 2.997(R)| FAST |spec_clk | 0.000|
spec_aux3_o | 15.826(R)| SLOW | 5.584(R)| FAST |spec_clk | 0.000|
spec_aux4_o | 14.681(R)| SLOW | 6.332(R)| FAST |spec_clk | 0.000|
pll_sdi_o | 19.174(R)| SLOW | 6.499(R)| FAST |spec_clk | 0.000|
spec_aux2_o | 18.339(R)| SLOW | 6.040(R)| FAST |spec_clk | 0.000|
spec_aux3_o | 15.031(R)| SLOW | 6.706(R)| FAST |spec_clk | 0.000|
spec_aux4_o | 8.266(R)| SLOW | 3.014(R)| FAST |spec_clk | 0.000|
spec_led_red_o | 8.412(R)| SLOW | 3.209(R)| FAST |spec_clk | 0.000|
tdc_led_trig1_o| 8.381(R)| SLOW | 3.128(R)| FAST |spec_clk | 0.000|
---------------+-----------------+------------+-----------------+------------+------------------+--------+
......@@ -139,9 +139,9 @@ Clock to Setup on destination clock spec_clk_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
spec_clk_i | 7.369| | | |
tdc_clk_n_i | 4.475| | | |
tdc_clk_p_i | 4.475| | | |
spec_clk_i | 7.332| | | |
tdc_clk_n_i | 5.950| | | |
tdc_clk_p_i | 5.950| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc_clk_n_i
......@@ -149,9 +149,9 @@ Clock to Setup on destination clock tdc_clk_n_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
spec_clk_i | 7.224| | | |
tdc_clk_n_i | 4.728| | | |
tdc_clk_p_i | 4.728| | | |
spec_clk_i | 11.383| | | |
tdc_clk_n_i | 4.898| | | |
tdc_clk_p_i | 4.898| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc_clk_p_i
......@@ -159,9 +159,9 @@ Clock to Setup on destination clock tdc_clk_p_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
spec_clk_i | 7.224| | | |
tdc_clk_n_i | 4.728| | | |
tdc_clk_p_i | 4.728| | | |
spec_clk_i | 11.383| | | |
tdc_clk_n_i | 4.898| | | |
tdc_clk_p_i | 4.898| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
......@@ -169,30 +169,30 @@ Pad to Pad
Source Pad |Destination Pad | Delay |
---------------+----------------+---------+
pll_ld_i |spec_led_green_o| 12.366|
rst_n_a_i |spec_aux5_o | 11.006|
rst_n_a_i |spec_aux5_o | 14.919|
spec_aux0_i |tdc_led_trig3_o | 15.691|
spec_aux0_i |tdc_led_trig4_o | 15.691|
spec_aux0_i |tdc_led_trig5_o | 17.050|
spec_aux1_i |spec_aux5_o | 8.917|
spec_aux1_i |spec_aux5_o | 8.387|
---------------+----------------+---------+
Timing summary:
---------------
Timing errors: 9 Score: 17366 (Setup/Max: 17366, Hold: 0)
Timing errors: 18 Score: 19904 (Setup/Max: 19904, Hold: 0)
Constraints cover 5229 paths, 0 nets, and 709 connections
Constraints cover 5298 paths, 0 nets, and 836 connections
Design statistics:
Minimum period: 11.929ns (Maximum frequency: 83.829MHz)
Maximum combinational path delay: 17.050ns
Maximum path delay from/to any node: 11.929ns
Minimum input required time before clock: 20.944ns
Maximum output delay after clock: 17.070ns
Minimum input required time before clock: 13.053ns
Maximum output delay after clock: 19.174ns
Analysis completed Fri Jul 15 19:32:08 2011
Analysis completed Mon Jul 18 09:45:06 2011
--------------------------------------------------------------------------------
Trace Settings:
......
This diff is collapsed.
Release 13.1 - par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Fri Jul 15 19:32:02 2011
Mon Jul 18 09:44:59 2011
All signals are completely routed.
......
#Release 13.1 - par O.40d (lin64)
#Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
#Fri Jul 15 19:32:01 2011
#Mon Jul 18 09:44:59 2011
#
## NOTE: This file is designed to be imported into a spreadsheet program
......@@ -190,7 +190,7 @@ F14,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,,
F15,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
F16,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,,
F17,,IOBS,IO_L51N_0,UNUSED,,0,,,,,,,,,
F18,spec_aux4_o,IOB,IO_L1P_A25_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,NO,NONE,
F18,spec_aux4_o,IOB,IO_L1P_A25_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,YES,NONE,
F19,,IOBS,IO_L1N_A24_VREF_1,UNUSED,,1,,,,,,,,,
F20,spec_aux3_o,IOB,IO_L29N_A22_M1A14_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,NO,NONE,
F21,p2l_data_i(14),IOB,IO_L31P_A19_M1CKE_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
......@@ -213,7 +213,7 @@ G15,,IOBS,IO_L49N_0,UNUSED,,0,,,,,,,,,
G16,,IOBM,IO_L51P_0,UNUSED,,0,,,,,,,,,
G17,,,TDO,,,,,,,,,,,,
G18,,,GND,,,,,,,,,,,,
G19,spec_aux2_o,IOB,IO_L29P_A23_M1A13_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,YES,NONE,
G19,spec_aux2_o,IOB,IO_L29P_A23_M1A13_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,NO,NONE,
G20,p2l_data_i(6),IOB,IO_L35P_A11_M1A7_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
G21,,,VCCO_1,,,1,,,,,1.80,,,,
G22,p2l_data_i(5),IOB,IO_L35N_A10_M1A2_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
......
Release 13.1 - par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Fri Jul 15 19:32:02 2011
Mon Jul 18 09:44:59 2011
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......@@ -191,7 +191,7 @@ Pinout by Pin Number:
|F15 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | |
|F16 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | |
|F17 | |IOBS |IO_L51N_0 |UNUSED | |0 | | | | | | | | |
|F18 |spec_aux4_o |IOB |IO_L1P_A25_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |NO |NONE |
|F18 |spec_aux4_o |IOB |IO_L1P_A25_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |YES |NONE |
|F19 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | |
|F20 |spec_aux3_o |IOB |IO_L29N_A22_M1A14_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |NO |NONE |
|F21 |p2l_data_i(14) |IOB |IO_L31P_A19_M1CKE_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE |
......@@ -214,7 +214,7 @@ Pinout by Pin Number:
|G16 | |IOBM |IO_L51P_0 |UNUSED | |0 | | | | | | | | |
|G17 | | |TDO | | | | | | | | | | | |
|G18 | | |GND | | | | | | | | | | | |
|G19 |spec_aux2_o |IOB |IO_L29P_A23_M1A13_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |YES |NONE |
|G19 |spec_aux2_o |IOB |IO_L29P_A23_M1A13_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |NO |NONE |
|G20 |p2l_data_i(6) |IOB |IO_L35P_A11_M1A7_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE |
|G21 | | |VCCO_1 | | |1 | | | | |1.80 | | | |
|G22 |p2l_data_i(5) |IOB |IO_L35N_A10_M1A2_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE |
......
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>269</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>709</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>709</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>601</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>287</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>836</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>836</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>711</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>9.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>10.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>10.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>11.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>12.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>17.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>20.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>12.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>17.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>20.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>20.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>20.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>20.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>12.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>7.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>5.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>8.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>1.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0271</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0277</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
......@@ -14,7 +14,7 @@ Name Total elements Utilization Notes
REGISTERS 92 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 92 (18.70 % Utilization)
Total SEQUENTIAL ELEMENTS in the block top_tdc: 92 (18.04 % Utilization)
COMBINATIONAL LOGIC
......@@ -22,13 +22,13 @@ COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 178 100 %
LUTS 196 100 %
MUXCY 70 100 %
XORCY 71 100 %
MULT18x18/MULT18x18S 1 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 320 (65.04 % Utilization)
Total COMBINATIONAL LOGIC in the block top_tdc: 338 (66.27 % Utilization)
MEMORY ELEMENTS
......@@ -69,7 +69,7 @@ Name Total elements Utilization Notes
-------------------------------------------------
PADS 66 100 %
=================================================
Total IO PADS in the block top_tdc: 66 (13.41 % Utilization)
Total IO PADS in the block top_tdc: 66 (12.94 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
......
......@@ -16,7 +16,7 @@ Name Total elements Utilization Notes
REGISTERS 92 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 92 (18.70 % Utilization)
Total SEQUENTIAL ELEMENTS in the block top_tdc: 92 (18.04 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
......@@ -25,13 +25,13 @@ COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 178 100 %
LUTS 196 100 %
MUXCY 70 100 %
XORCY 71 100 %
MULT18x18/MULT18x18S 1 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 320 (65.04 % Utilization)
Total COMBINATIONAL LOGIC in the block top_tdc: 338 (66.27 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
......@@ -76,7 +76,7 @@ Name Total elements Utilization Notes
-------------------------------------------------
PADS 66 100 %
=================================================
Total IO PADS in the block top_tdc: 66 (13.41 % Utilization)
Total IO PADS in the block top_tdc: 66 (12.94 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
......
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/run_options.txt
#-- Written on Fri Jul 15 19:30:52 2011
#-- Written on Mon Jul 18 09:43:56 2011
#project files
......
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/scratchproject.prs
#-- Written on Fri Jul 15 19:30:52 2011
#-- Written on Mon Jul 18 09:43:56 2011
#project files
......
......@@ -37,10 +37,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 311956 kilobytes
Total memory usage is 312080 kilobytes
Writing NGD file "syn_tdc.ngd" ...
Total REAL time to NGDBUILD completion: 9 sec
Total REAL time to NGDBUILD completion: 10 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "syn_tdc.bld"...
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -8,7 +8,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Jul 15 19:31:22 2011
Mapped Date : Mon Jul 18 09:44:18 2011
Mapping design into LUTs...
Writing file syn_tdc.ngm...
......@@ -19,59 +19,59 @@ INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 8 secs
Total CPU time at the beginning of Placer: 8 secs
Total CPU time at the beginning of Placer: 7 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:8e69df18) REAL time: 9 secs
Phase 1.1 Initial Placement Analysis (Checksum:8e53cbb8) REAL time: 9 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 135 IOs, 134 are locked
and 1 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:8e69df18) REAL time: 9 secs
Phase 2.7 Design Feasibility Check (Checksum:8e53cbb8) REAL time: 9 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:8e69df18) REAL time: 9 secs
Phase 3.31 Local Placement Optimization (Checksum:8e53cbb8) REAL time: 9 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:4ab12e71) REAL time: 14 secs
(Checksum:5135e245) REAL time: 14 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:4ab12e71) REAL time: 14 secs
Phase 5.36 Local Placement Optimization (Checksum:5135e245) REAL time: 14 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:4ab12e71) REAL time: 14 secs
Phase 6.30 Global Clock Region Assignment (Checksum:5135e245) REAL time: 14 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:7f94c7c9) REAL time: 14 secs
Phase 7.3 Local Placement Optimization (Checksum:31c1d851) REAL time: 14 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:7f94c7c9) REAL time: 14 secs
Phase 8.5 Local Placement Optimization (Checksum:31c1d851) REAL time: 14 secs
Phase 9.8 Global Placement
..............
......................
................
........
Phase 9.8 Global Placement (Checksum:e99791f2) REAL time: 15 secs
............
.................................................................
.......................
...
Phase 9.8 Global Placement (Checksum:78e18431) REAL time: 15 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:e99791f2) REAL time: 15 secs
Phase 10.5 Local Placement Optimization (Checksum:78e18431) REAL time: 15 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:708689a4) REAL time: 16 secs
Phase 11.18 Placement Optimization (Checksum:fe7345b3) REAL time: 17 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:708689a4) REAL time: 16 secs
Phase 12.5 Local Placement Optimization (Checksum:fe7345b3) REAL time: 17 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:6ccb73df) REAL time: 16 secs
Phase 13.34 Placement Validation (Checksum:f80c1b30) REAL time: 17 secs
Total REAL time to Placer completion: 16 secs
Total CPU time to Placer completion: 15 secs
Total REAL time to Placer completion: 17 secs
Total CPU time to Placer completion: 17 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <p2l_data_i(0)_IBUF> is incomplete. The
......@@ -227,11 +227,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 177 out of 27,288 1%
Number used as logic: 176 out of 27,288 1%
Number using O6 output only: 108
Number using O5 output only: 30
Number using O5 and O6: 38
Number of Slice LUTs: 193 out of 27,288 1%
Number used as logic: 192 out of 27,288 1%
Number using O6 output only: 121
Number using O5 output only: 31
Number using O5 and O6: 40
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 1
......@@ -240,11 +240,11 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 63 out of 6,822 1%
Number of LUT Flip Flop pairs used: 179
Number with an unused Flip Flop: 93 out of 179 51%
Number with an unused LUT: 2 out of 179 1%
Number of fully used LUT-FF pairs: 84 out of 179 46%
Number of occupied Slices: 80 out of 6,822 1%
Number of LUT Flip Flop pairs used: 195
Number with an unused Flip Flop: 109 out of 195 55%
Number with an unused LUT: 2 out of 195 1%
Number of fully used LUT-FF pairs: 84 out of 195 43%
Number of unique control sets: 6
Number of slice register sites lost
to control set restrictions: 18 out of 54,576 1%
......@@ -289,11 +289,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.20
Average Fanout of Non-Clock Nets: 2.34