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VME FMC Carrier VFC
Commit 8cac29ef authored by Andrea Boccardi's avatar Andrea Boccardi
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minor changes in the structure of the project

parent b46b223e
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trunk/hdl/design/Generic4InputRegs.v
View file @ 8cac29ef
module Generic4InputRegs (
input Rst_irq,
input Clk_ik,
input Cyc_i,
input Stb_i,
input We_i,
input [1:0] Adr_ib2,
output reg [31:0] Dat_oab32,
output Ack_oa,
......
trunk/hdl/design/InterruptManagerWB.v
View file @ 8cac29ef
......@@ -62,7 +62,7 @@ always @(posedge Clk_ik) begin
end
end
assign asynch_clk_change = clrn && ~interrupt_in[6];
assign asynch_clk_change = ~Rst_irq && ~interrupt_in[6];
initial osc_clk = 1;
......
trunk/hdl/design/Monostable.v
View file @ 8cac29ef
......@@ -10,7 +10,7 @@ reg [2:0] AsynchInAX_db3 = 2'b0;
always @(posedge AsynchIn_ia) AsynchIn_ax <= #1 ~AsynchIn_ax;
always @(posedge Clk_ik) AsynchInAX_db3 <= #1 {AsynchInAX_db3[1:0], AsynchIn_ax};
wire SynchIn_p = ^AsynchInAX_qdb3[2:1];
wire SynchIn_p = ^AsynchInAX_db3[2:0];
reg [g_CounterBits-1:0] Counter_c = 'b0;
......
trunk/hdl/design/Slv2SerWB.v
View file @ 8cac29ef
......@@ -25,14 +25,12 @@ reg [31:0] DatOutShReg_b32 = 32'h0,
CntrlShReg_b32 = 32'h2;
reg [31:0] StbShReg_b32 = 32'h2;
reg StbI_d, AckI_d;
reg StbI_d;
always @(posedge Clk_ik)
if (Rst_irq) begin
AckI_d <= `dly 1'b0;
StbI_d <= `dly 1'b0;
end else begin
AckI_d <= `dly Ack_i;
StbI_d <= `dly Stb_i;
end
......
trunk/hdl/design/SpiMasterWB.v
View file @ 8cac29ef
......@@ -40,7 +40,6 @@
reg [31:0] Config2_qb32,
ShiftOut_qb32,
ShiftIn_qb32,
a_Status_b32,
Config1_qb32;
wire a_CPol = Config1_qb32[31];
......@@ -65,6 +64,7 @@ reg [2:0] State_a,
reg [15:0] TimeCounter_cb16;
reg [11:0] TxCounter_cb12;
reg WriteAck_q, StartTx_q;
always @(posedge Clk_ik)
if (Rst_irq) State_q <= `s_Idle;
......@@ -86,8 +86,6 @@ always @* begin
endcase
end
reg WriteAck_q, StartTx_q;
assign MoSi_o = a_Lsb1St ? ShiftOut_qb32[0] : ShiftOut_qb32[31];
always @(posedge Clk_ik) begin
......@@ -110,7 +108,7 @@ always @(posedge Clk_ik) begin
end else case (State_q)
`s_Idle: begin
SClk_o <= a_CPol;
SS_onb32 <= 32'h_FFFF_FFFF;
SS_onb32 <= 32'hFFFF_FFFF;
TimeCounter_cb16 <= 'h0;
TxCounter_cb12 <= 'h0;
ModuleIdle_o <= State_a==`s_Idle;
......
trunk/hdl/design/SystemFpga.v
View file @ 8cac29ef
......@@ -155,14 +155,16 @@ module SystemFpga (
`define dly 1
wire [31:0] InterruptConfigReg_b32, GenericOutputReg1, PllConfigBits_b32, GenericOutputReg3;
wire [31:0] DatGenericOutputRegsrO_b32;
wire StbGenericOutputRegs, AckGenericOutputRegs;
wire VmeAccessForLed;
wire RstForLed;
//####################################
// FP Leds
//####################################
wire VmeAccessForLed;
wire RstForLed;
Monostable i_VmeAccessMonostable(
.AsynchIn_ia(StbMaster),
.Clk_ik(Clk_k),
......@@ -178,16 +180,16 @@ assign FpLed_onb8[1] = (~&VmeIrq_ob7) ? 1'b0 : 1'bz;
assign FpLed_onb8[2] = (^{VmeGa_ib5n, ~VmeGaP_in} | ~UseGa_i) ? 1'b0 : 1'bz;
assign FpLed_onb8[3] = RstForLed ? 1'b0 : 1'bz;
wire Si57xDivided = Si57xDivider_c[21];
reg [21:0] Si57xDivider_c = 'd0;
wire Si57xDivided = Si57xDivider_c[21];
always @(posedge Si57x_ik) Si57xDivider_c <= #`dly Si57xDivider_c + 1'b1;
wire VcTcXoDivided = VcTcXoDivider_c[21];
reg [21:0] VcTcXoDivider_c = 'd0;
wire VcTcXoDivided = VcTcXoDivider_c[21];
always @(posedge VcTcXo_ik) VcTcXoDivider_c <= #`dly VcTcXoDivider_c + 1'b1;
wire VmeSysClkDivided = VmeSysClkDivider_c[21];
reg [21:0] VmeSysClkDivider_c = 'd0;
wire VmeSysClkDivided = VmeSysClkDivider_c[21];
always @(posedge VmeSysClk_ik) VmeSysClkDivider_c <= #`dly VmeSysClkDivider_c + 1'b1;
reg a_FpLed7;
......@@ -216,13 +218,7 @@ assign FpGpIo34OutputMode_o = 1'b1;
// Clock
//####################################
reg Clk_k;
always @* case(Switch_ib2)
2'b00: Clk_k = Si57x_ik;
2'b01: Clk_k = VcTcXo_ik;
2'b10: Clk_k = VmeSysClk_ik;
default: Clk_k = VcTcXo_ik;
endcase
wire Clk_k= Si57x_ik;
//#####################################
// Reset Signal Generation
......@@ -246,10 +242,10 @@ always @(posedge Clk_k) Rst_rq <= #`dly ~DeboucedPushButton_q || ~a_VmeSysReset_
// VME Interface
//#####################################
wire SpiIdle, SpiWaitingData;
wire IntAcknowledged;
wire AssertInterrupt;
wire VmeDtAck_n, VmeDOe;
wire RdReg, WrReg;
wire [7:1] VmeIrq_b7n;
assign VmeDtAck_on = 1'b0;
......@@ -360,11 +356,6 @@ AddressDecoderWBSys i_AddressDecoderWB(
// GenericOutput Registers
//#####################################
wire [31:0] InterruptConfigReg_b32, GenericOutputReg1, PllConfigBits_b32, GenericOutputReg3;
wire [31:0] DatGenericOutputRegsrO_b32;
wire StbGenericOutputRegs, AckGenericOutputRegs;
Generic4OutputRegs #(.Reg2Default(32'h8888)) i_Generic4OutputRegs(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
......@@ -391,10 +382,8 @@ wire StbGenericInputRegs, AckGenericInputRegs;
Generic4InputRegs i_Generic4InputRegs(
.Rst_irq(Rst_rq),
.Clk_ik(Clk_k),
.Cyc_i(Cyc),
.Stb_i(StbGenericInputRegs),
.We_i(We),
.Adr_ib2(Adr_b22[1:0]),
.Dat_oab32(DatGenericInputRegsrO_b32),
.Ack_oa(AckGenericInputRegs),
......@@ -487,7 +476,6 @@ assign PllDacSynch_on = SpiSS_nb32[0];
assign PllDacDin_o = SpiMoSi;
assign PllDacSClk_ok = SpiSClk_k;
wire SpiIdle, SpiWaitingData;
SpiMasterWB i_SpiMasterWB(
.Rst_irq(Rst_rq),
......@@ -529,6 +517,7 @@ assign PllDdsPd_on = PllConfigBits_b32[2];
assign PllDdsSynch_on = PllConfigBits_b32[1];
assign PllDdsReset_orn = PllConfigBits_b32[0];
assign PllStatusBits_b32[31:16] = 16'h0;
assign PllStatusBits_b32[15] = PllFmc1Ld_i;
assign PllStatusBits_b32[14] = PllFmc1Status_i;
assign PllStatusBits_b32[13] = PllFmc1RefMon_i;
......
trunk/hdl/design/VmeInterfaceWB.v
View file @ 8cac29ef
......@@ -57,9 +57,6 @@ wire [4:0] base_addr;
wire gap_error;
wire selected;
reg dav_reg;
reg [31:0] data_in_reg;
wire valid_am;
reg [2:0] state;
......
trunk/software/VfcRegistersMap.py
View file @ 8cac29ef
from VmeFunctions import *
class VfcRegisters:
###############################################################################
###############################################################################
# REGISTER SPACE
###############################################################################
###############################################################################
def __init__(self, Slot):
self.Slot = Slot
BoardBaseAddress = Slot*2**24
......
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