Merge branch 'fix_cdc_constraints' into 'master'

Fix to CDC constraints generator matching filters See merge request !43

Merge branch 'fix_cdc_constraints' into 'master'
Fix to CDC constraints generator matching filters See merge request !43
490af642 · Tristan Gingold · 14a5f2f2 · 19e2882a · 490af642 · 490af642
Commit 490af642 authored Mar 13, 2024 by Tristan Gingold
4 changed files
--- a/modules/common/xdc/gc_reset_multi_aasd.xdc
+++ b/modules/common/xdc/gc_reset_multi_aasd.xdc
+# the "-quiet" option is added for the use case where this module is added to
+# the project, but not instatiated (e.g. because of generic settings)
+# in that case Vivado would throw critical warnings during P&$
+
+set_false_path -quiet -to [get_pins -hierarchical *rst_chains_reg[*]/CLR] 
--- a/modules/common/xdc/gc_sync.xdc
+++ b/modules/common/xdc/gc_sync.xdc
+# Timing constrains for basic 1 bit synchroniser.
+# In many cases this could be solved with simple set_false_path, but in some
+# cases this module is used in more time-critical applications, eg. inferred FIFO.
+# In that case it makes sense to apply some max_delay constraint.
+#
+# You can always override any of these max_delay constraints in your global XDC
+# with set_false_path because it has the highest priority.
+
+set clk [get_clocks -of_objects [get_ports clk_i]]
+set clk_period [get_property PERIOD $clk]
+
+# ATTENTION: we can't use "all_fanin" to find the source register because
+# apparently this command doesn't traverse outside of scoped reference (even with -flat switch)
+# This method won't work properly if there's a combinational path between a source and target FF;
+# but in a proper CDC circuit it's forbidded to have logic between FFs anyway!
+set dst_ff [get_pins sync_*.sync0_*/D]
+set src_ff [get_cells -of_objects [get_pins -filter {IS_LEAF && DIRECTION == OUT} -of_objects [get_nets -segments -of_objects $dst_ff]]]
+
+# We use -quiet switch, because otherwise Vivado will throw critical warning
+# if module is not used in the project (e.g. due to generics)
+set_max_delay $clk_period -quiet -datapath_only -from $src_ff -to $dst_ff
--- a/modules/common/xdc/gc_sync_register.xdc
+++ b/modules/common/xdc/gc_sync_register.xdc
+# Timing constrains for basic bit vector synchroniser.
+# 
+# This is similar to gc_sync, but vector synchronisation is usually more tricky.
+# Usually you really want to limit bus skew and delay to one clock cycle.
+#
+# You can always override any of these max_delay constraints in your global XDC
+# with set_false_path because it has the highest priority.
+
+set clk [get_clocks -of_objects [get_ports clk_i]]
+set clk_period [get_property PERIOD $clk]
+
+# ATTENTION: we can't use "all_fanin" to find the source register because
+# apparently this command doesn't traverse outside of scoped reference (even with -flat switch)
+# This method won't work properly if there's a combinational path between a source and target FF;
+# but in a proper CDC circuit it's forbidded to have logic between FFs anyway!
+set dst_ff [get_pins sync0_*[*]/D]
+set src_ff [get_cells -of_objects [get_pins -filter {IS_LEAF && DIRECTION == OUT} -of_objects [get_nets -segments -of_objects $dst_ff]]]
+
+# We use -quiet switch, because otherwise Vivado will throw critical warning
+# if module is not used in the project (e.g. due to generics)
+set_max_delay $clk_period -quiet -datapath_only -from $src_ff -to $dst_ff
+set_bus_skew $clk_period -quiet -from $src_ff -to $dst_ff
--- a/tools/generate_cdc_constraints.tcl
+++ b/tools/generate_cdc_constraints.tcl
@@ -270,7 +270,7 @@ proc generate_gc_reset_multi_aasd_constraints { f_out } {
 }

 proc generate_gc_falsepath_waiver_constraints { f_out } {
-    set the_cells [ get_cells -hier -filter { REF_NAME=~gc_falsepath_waiver* } ]
+    set the_cells [ get_cells -hier -filter { REF_NAME==gc_falsepath_waiver || ORIG_REF_NAME==gc_falsepath_waiver} ]
    set count 0

    foreach cell $the_cells {