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Hdlmake
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f9366683ba937b79eb6c40aeb08abfdd7ddd499f
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hdl-make
tests
counter
sim
vivado
verilog
Manifest.py
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Split Vivado into two different tool modules for synthesis and simulation
· f5fd4714
Javier D. Garcia-Lasheras
authored
May 25, 2017
f5fd4714
Manifest.py
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