Commit 0383ad54 authored by Tristan Gingold's avatar Tristan Gingold

Add ManualFile to manually give provided unit and dependencies

parent 10eed1d9
......@@ -31,7 +31,7 @@ import sys
from ..tools.load_tool import load_syn_tool, load_sim_tool
from ..util import shell
from ..sourcefiles import new_dep_solver as dep_solver
from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SVFile, ParamFile
from ..sourcefiles.srcfile import ParamFile, SourceFile, ManualFile
from ..sourcefiles.sourcefileset import SourceFileSet
from ..module.module import Module, ModuleArgs
from ..sourcefiles import systemlibs
......@@ -133,19 +133,16 @@ class Action(object):
all_files = self._build_complete_file_set()
for file_aux in all_files:
if self.tool:
if any(isinstance(file_aux, file_type)
for file_type in self.tool.get_parseable_files()):
if isinstance(file_aux, tuple(self.tool.get_parseable_files())):
self.parseable_fileset.add(file_aux)
elif any(isinstance(file_aux, file_type)
for file_type in self.tool.get_privative_files()):
elif isinstance(file_aux, tuple(self.tool.get_privative_files())):
self.privative_fileset.add(file_aux)
else:
logging.debug("File not supported by the tool: %s",
file_aux.path)
else:
# Not usual case: tool is not known
if any(isinstance(file_aux, file_type)
for file_type in [VHDLFile, VerilogFile, SVFile]):
if isinstance(file_aux, (SourceFile, ManualFile)):
self.parseable_fileset.add(file_aux)
else:
self.privative_fileset.add(file_aux)
......
......@@ -177,9 +177,17 @@ class Module(object):
"""Get a list with only the valid absolute paths from the provided"""
paths = []
for filepath in list_of_paths:
files = self._check_filepath(filepath)
for f in files:
paths.append(f)
if isinstance(filepath, tuple):
# A tuple of the form (filename, provide [, dependencies])
files = self._check_filepath(filepath[0])
assert len(files) == 1
files.append(path_mod.flatten_list(filepath[1]))
files.extend(list(filepath[2:]))
paths.append(tuple(files))
else:
files = self._check_filepath(filepath)
for f in files:
paths.append(f)
return paths
def _create_file_list_from_paths(self, paths):
......@@ -187,7 +195,7 @@ class Module(object):
Build a Source File Set containing the files indicated by the
provided list of paths
"""
from ..sourcefiles.srcfile import create_source_file
from ..sourcefiles.srcfile import create_source_file, create_source_file_with_deps
from ..sourcefiles.sourcefileset import SourceFileSet
srcs = SourceFileSet()
# Check if this is the top module and grab the include_dirs
......@@ -196,21 +204,28 @@ class Module(object):
else:
include_dirs = self.top_manifest.manifest_dict.get(
'include_dirs', [])
for path_aux in paths:
if os.path.isdir(path_aux):
for path in paths:
if isinstance(path, tuple):
assert 1 < len(path) < 4
pathname=path[0]
provide=path[1]
depends=path[2] if len(path) > 2 else []
srcs.add(create_source_file_with_deps(path=pathname,
module=self,
provide=provide,
depends=depends))
elif os.path.isdir(path):
# If a path is a dir, add all the files of that dir.
dir_ = os.listdir(path_aux)
dir_ = os.listdir(path)
for f_dir in dir_:
f_dir = os.path.join(self.path, path_aux, f_dir)
f_dir = os.path.join(self.path, path, f_dir)
if not os.path.isdir(f_dir):
srcs.add(create_source_file(path=f_dir,
module=self,
library=self.library,
include_dirs=include_dirs))
else:
srcs.add(create_source_file(path=path_aux,
srcs.add(create_source_file(path=path,
module=self,
library=self.library,
include_dirs=include_dirs))
return srcs
......
......@@ -205,3 +205,22 @@ class DepFile(File):
return True
stack.pop()
return False
class ManualFile(DepFile):
"""Class that serves as base to binary HDL files with
dependencies and provided units manually added by the user"""
def __init__(self, path, module, provide=None, depends=[]):
DepFile.__init__(self, path=path, module=module)
self.provide_units = provide
self.depends_units = depends
def parse(self, graph):
for unit in self.provide_units:
graph.add_provide(self, DepRelation(unit, self.library, DepRelation.ENTITY))
for unit in self.depends_units:
graph.add_require(self, DepRelation(unit, self.library, DepRelation.ENTITY))
......@@ -91,7 +91,7 @@ def parse_source_files(graph, fileset):
for investigated_file in fileset:
assert isinstance(investigated_file, DepFile)
logging.debug("PARSING SOURCE FILE: %s", investigated_file)
investigated_file.parser.parse(investigated_file, graph)
investigated_file.parse(graph)
if logging.root.level >= logging.DEBUG:
for r in investigated_file.provides:
logging.debug("PROVIDE %s", r)
......
......@@ -29,7 +29,7 @@ import os
import logging
from ..util import path as path_mod
from .dep_file import DepFile, File, ParamFile
from .dep_file import DepFile, File, ParamFile, ManualFile
import six
......@@ -38,9 +38,9 @@ class SourceFile(DepFile):
"""This is a class acting as a base for the different
HDL sources files, i.e. those that can be parsed"""
def __init__(self, path, module, library):
def __init__(self, path, module):
assert isinstance(path, six.string_types)
self.library = library
self.library = module.library
DepFile.__init__(self, path=path, module=module)
def __hash__(self):
......@@ -49,6 +49,9 @@ class SourceFile(DepFile):
s += self.library
return hash(s)
def parse(self, graph):
assert False, "to be implemented"
# SOURCE FILES
......@@ -56,22 +59,28 @@ class VHDLFile(SourceFile):
"""This is the class providing the generic VHDL file"""
def __init__(self, path, module, library=None):
SourceFile.__init__(self, path=path, module=module, library=library)
def __init__(self, path, module):
SourceFile.__init__(self, path=path, module=module)
def parse(self, graph):
from .vhdl_parser import VHDLParser
self.parser = VHDLParser()
self.parser.parse(self, graph)
class VerilogFile(SourceFile):
"""This is the class providing the generic Verilog file"""
def __init__(self, path, module, library=None, include_dirs=None):
SourceFile.__init__(self, path=path, module=module, library=library)
from .vlog_parser import VerilogParser
def __init__(self, path, module, include_dirs=None):
SourceFile.__init__(self, path=path, module=module)
self.include_dirs = include_dirs[:] if include_dirs else []
self.include_dirs.append(path_mod.relpath(self.dirname))
def parse(self, graph):
from .vlog_parser import VerilogParser
self.parser = VerilogParser()
self.parser.parse(self, graph)
class SVFile(VerilogFile):
......@@ -124,7 +133,7 @@ class XCOFile(File):
pass
class NGCFile(File):
class NGCFile(ManualFile):
"""Xilinx Generated Netlist File"""
pass
......@@ -151,13 +160,11 @@ class MIFFile(File):
class RAMFile(File):
"""Xilinx RAM File"""
pass
class HEXFile(SourceFile):
"""Memory initialization binary file in .hex format"""
pass
......@@ -179,19 +186,19 @@ class VEOFile(File):
class XCIFile(SourceFile):
"""Xilinx Core IP File"""
def __init__(self, path, module, library=None):
SourceFile.__init__(self, path=path, module=module, library=library)
def parse(self, graph):
from .xci_parser import XCIParser
self.parser = XCIParser()
self.parser.parse(self, graph)
class BDFile(SourceFile):
"""Xilinx Block Design"""
def __init__(self, path, module, library=None):
SourceFile.__init__(self, path=path, module=module, library=library)
def parse(self, graph):
from .bd_parser import BDParser
self.parser = BDParser()
self.parser.parse(self, graph)
XILINX_FILE_DICT = {
......@@ -384,7 +391,7 @@ SV_EXTENSIONS = (
'svh')
def create_source_file(path, module, library=None, include_dirs=None):
def create_source_file(path, module, include_dirs=None):
"""Function that analyzes the given arguments and returns a new HDL source
file of the appropriated type"""
assert path
......@@ -395,19 +402,20 @@ def create_source_file(path, module, library=None, include_dirs=None):
extension = extension[1:]
logging.debug("add file " + path)
if extension in VHDL_EXTENSIONS:
if extension in ("ngc", ):
logging.warning("file %s in %s has no explicit provided units, rewrite as '(filename, unit)'",
path, module)
new_file = File(path=path, module=module)
elif extension in VHDL_EXTENSIONS:
new_file = VHDLFile(path=path,
module=module,
library=library)
module=module)
elif extension in VERILOG_EXTENSIONS:
new_file = VerilogFile(path=path,
module=module,
library=library,
include_dirs=include_dirs)
elif extension in SV_EXTENSIONS:
new_file = SVFile(path=path,
module=module,
library=library,
include_dirs=include_dirs)
elif extension == 'wb':
new_file = WBGenFile(path=path, module=module)
......@@ -416,9 +424,9 @@ def create_source_file(path, module, library=None, include_dirs=None):
elif extension == 'sdc':
new_file = SDCFile(path=path, module=module)
elif extension == 'xci':
new_file = XCIFile(path=path, module=module, library=library)
new_file = XCIFile(path=path, module=module)
elif extension == 'cxf':
new_file = CXFFile(path=path, module=module, library=library)
new_file = CXFFile(path=path, module=module)
elif extension in XILINX_FILE_DICT:
new_file = XILINX_FILE_DICT[extension](path=path, module=module)
elif extension in ALTERA_FILE_DICT:
......@@ -430,3 +438,19 @@ def create_source_file(path, module, library=None, include_dirs=None):
else:
raise Exception("Unknown extension '{}' for file {}".format(extension, path))
return new_file
def create_source_file_with_deps(path, module, provide, depends):
"""Function that analyzes the given arguments and returns a new HDL source
file of the appropriated type"""
assert path
assert os.path.isabs(path)
_, extension = os.path.splitext(path)
assert extension[0] == '.'
# Remove '.'
extension = extension[1:]
logging.debug("add file with deps) " + path)
if extension == 'ngc':
return NGCFile(path, module, provide, depends)
raise Exception("Unknown extension '{}' for file {} (with deps)".format(extension, path))
......@@ -78,7 +78,8 @@ class ToolISE(MakefileSyn):
HDL_FILES = {
VHDLFile: 'HDL_FILES[VHDLFile] - NEEDS SETTING!!!',
VerilogFile: _ISE_ADD_SRCFILE,
SVFile: _ISE_ADD_SRCFILE}
SVFile: _ISE_ADD_SRCFILE,
NGCFile: None}
......
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