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Hdlmake
Commit 0383ad54 authored by Tristan Gingold's avatar Tristan Gingold
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Add ManualFile to manually give provided unit and dependencies

parent 10eed1d9
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Showing with 99 additions and 43 deletions
hdlmake/action/action.py
View file @ 0383ad54
...@@ -31,7 +31,7 @@ import sys ...@@ -31,7 +31,7 @@ import sys
from ..tools.load_tool import load_syn_tool, load_sim_tool from ..tools.load_tool import load_syn_tool, load_sim_tool
from ..util import shell from ..util import shell
from ..sourcefiles import new_dep_solver as dep_solver from ..sourcefiles import new_dep_solver as dep_solver
from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SVFile, ParamFile from ..sourcefiles.srcfile import ParamFile, SourceFile, ManualFile
from ..sourcefiles.sourcefileset import SourceFileSet from ..sourcefiles.sourcefileset import SourceFileSet
from ..module.module import Module, ModuleArgs from ..module.module import Module, ModuleArgs
from ..sourcefiles import systemlibs from ..sourcefiles import systemlibs
...@@ -133,19 +133,16 @@ class Action(object): ...@@ -133,19 +133,16 @@ class Action(object):
all_files = self._build_complete_file_set() all_files = self._build_complete_file_set()
for file_aux in all_files: for file_aux in all_files:
if self.tool: if self.tool:
if any(isinstance(file_aux, file_type) if isinstance(file_aux, tuple(self.tool.get_parseable_files())):
for file_type in self.tool.get_parseable_files()):
self.parseable_fileset.add(file_aux) self.parseable_fileset.add(file_aux)
elif any(isinstance(file_aux, file_type) elif isinstance(file_aux, tuple(self.tool.get_privative_files())):
for file_type in self.tool.get_privative_files()):
self.privative_fileset.add(file_aux) self.privative_fileset.add(file_aux)
else: else:
logging.debug("File not supported by the tool: %s", logging.debug("File not supported by the tool: %s",
file_aux.path) file_aux.path)
else: else:
# Not usual case: tool is not known # Not usual case: tool is not known
if any(isinstance(file_aux, file_type) if isinstance(file_aux, (SourceFile, ManualFile)):
for file_type in [VHDLFile, VerilogFile, SVFile]):
self.parseable_fileset.add(file_aux) self.parseable_fileset.add(file_aux)
else: else:
self.privative_fileset.add(file_aux) self.privative_fileset.add(file_aux)
......
hdlmake/module/module.py
View file @ 0383ad54
...@@ -177,9 +177,17 @@ class Module(object): ...@@ -177,9 +177,17 @@ class Module(object):
"""Get a list with only the valid absolute paths from the provided""" """Get a list with only the valid absolute paths from the provided"""
paths = [] paths = []
for filepath in list_of_paths: for filepath in list_of_paths:
files = self._check_filepath(filepath) if isinstance(filepath, tuple):
for f in files: # A tuple of the form (filename, provide [, dependencies])
paths.append(f) files = self._check_filepath(filepath[0])
assert len(files) == 1
files.append(path_mod.flatten_list(filepath[1]))
files.extend(list(filepath[2:]))
paths.append(tuple(files))
else:
files = self._check_filepath(filepath)
for f in files:
paths.append(f)
return paths return paths
def _create_file_list_from_paths(self, paths): def _create_file_list_from_paths(self, paths):
...@@ -187,7 +195,7 @@ class Module(object): ...@@ -187,7 +195,7 @@ class Module(object):
Build a Source File Set containing the files indicated by the Build a Source File Set containing the files indicated by the
provided list of paths provided list of paths
""" """
from ..sourcefiles.srcfile import create_source_file from ..sourcefiles.srcfile import create_source_file, create_source_file_with_deps
from ..sourcefiles.sourcefileset import SourceFileSet from ..sourcefiles.sourcefileset import SourceFileSet
srcs = SourceFileSet() srcs = SourceFileSet()
# Check if this is the top module and grab the include_dirs # Check if this is the top module and grab the include_dirs
...@@ -196,21 +204,28 @@ class Module(object): ...@@ -196,21 +204,28 @@ class Module(object):
else: else:
include_dirs = self.top_manifest.manifest_dict.get( include_dirs = self.top_manifest.manifest_dict.get(
'include_dirs', []) 'include_dirs', [])
for path_aux in paths: for path in paths:
if os.path.isdir(path_aux): if isinstance(path, tuple):
assert 1 < len(path) < 4
pathname=path[0]
provide=path[1]
depends=path[2] if len(path) > 2 else []
srcs.add(create_source_file_with_deps(path=pathname,
module=self,
provide=provide,
depends=depends))
elif os.path.isdir(path):
# If a path is a dir, add all the files of that dir. # If a path is a dir, add all the files of that dir.
dir_ = os.listdir(path_aux) dir_ = os.listdir(path)
for f_dir in dir_: for f_dir in dir_:
f_dir = os.path.join(self.path, path_aux, f_dir) f_dir = os.path.join(self.path, path, f_dir)
if not os.path.isdir(f_dir): if not os.path.isdir(f_dir):
srcs.add(create_source_file(path=f_dir, srcs.add(create_source_file(path=f_dir,
module=self, module=self,
library=self.library,
include_dirs=include_dirs)) include_dirs=include_dirs))
else: else:
srcs.add(create_source_file(path=path_aux, srcs.add(create_source_file(path=path,
module=self, module=self,
library=self.library,
include_dirs=include_dirs)) include_dirs=include_dirs))
return srcs return srcs
......
hdlmake/sourcefiles/dep_file.py
View file @ 0383ad54
...@@ -205,3 +205,22 @@ class DepFile(File): ...@@ -205,3 +205,22 @@ class DepFile(File):
return True return True
stack.pop() stack.pop()
return False return False
class ManualFile(DepFile):
"""Class that serves as base to binary HDL files with
dependencies and provided units manually added by the user"""
def __init__(self, path, module, provide=None, depends=[]):
DepFile.__init__(self, path=path, module=module)
self.provide_units = provide
self.depends_units = depends
def parse(self, graph):
for unit in self.provide_units:
graph.add_provide(self, DepRelation(unit, self.library, DepRelation.ENTITY))
for unit in self.depends_units:
graph.add_require(self, DepRelation(unit, self.library, DepRelation.ENTITY))
hdlmake/sourcefiles/new_dep_solver.py
View file @ 0383ad54
...@@ -91,7 +91,7 @@ def parse_source_files(graph, fileset): ...@@ -91,7 +91,7 @@ def parse_source_files(graph, fileset):
for investigated_file in fileset: for investigated_file in fileset:
assert isinstance(investigated_file, DepFile) assert isinstance(investigated_file, DepFile)
logging.debug("PARSING SOURCE FILE: %s", investigated_file) logging.debug("PARSING SOURCE FILE: %s", investigated_file)
investigated_file.parser.parse(investigated_file, graph) investigated_file.parse(graph)
if logging.root.level >= logging.DEBUG: if logging.root.level >= logging.DEBUG:
for r in investigated_file.provides: for r in investigated_file.provides:
logging.debug("PROVIDE %s", r) logging.debug("PROVIDE %s", r)
......
hdlmake/sourcefiles/srcfile.py
View file @ 0383ad54
...@@ -29,7 +29,7 @@ import os ...@@ -29,7 +29,7 @@ import os
import logging import logging
from ..util import path as path_mod from ..util import path as path_mod
from .dep_file import DepFile, File, ParamFile from .dep_file import DepFile, File, ParamFile, ManualFile
import six import six
...@@ -38,9 +38,9 @@ class SourceFile(DepFile): ...@@ -38,9 +38,9 @@ class SourceFile(DepFile):
"""This is a class acting as a base for the different """This is a class acting as a base for the different
HDL sources files, i.e. those that can be parsed""" HDL sources files, i.e. those that can be parsed"""
def __init__(self, path, module, library): def __init__(self, path, module):
assert isinstance(path, six.string_types) assert isinstance(path, six.string_types)
self.library = library self.library = module.library
DepFile.__init__(self, path=path, module=module) DepFile.__init__(self, path=path, module=module)
def __hash__(self): def __hash__(self):
...@@ -49,6 +49,9 @@ class SourceFile(DepFile): ...@@ -49,6 +49,9 @@ class SourceFile(DepFile):
s += self.library s += self.library
return hash(s) return hash(s)
def parse(self, graph):
assert False, "to be implemented"
# SOURCE FILES # SOURCE FILES
...@@ -56,22 +59,28 @@ class VHDLFile(SourceFile): ...@@ -56,22 +59,28 @@ class VHDLFile(SourceFile):
"""This is the class providing the generic VHDL file""" """This is the class providing the generic VHDL file"""
def __init__(self, path, module, library=None): def __init__(self, path, module):
SourceFile.__init__(self, path=path, module=module, library=library) SourceFile.__init__(self, path=path, module=module)
def parse(self, graph):
from .vhdl_parser import VHDLParser from .vhdl_parser import VHDLParser
self.parser = VHDLParser() self.parser = VHDLParser()
self.parser.parse(self, graph)
class VerilogFile(SourceFile): class VerilogFile(SourceFile):
"""This is the class providing the generic Verilog file""" """This is the class providing the generic Verilog file"""
def __init__(self, path, module, library=None, include_dirs=None): def __init__(self, path, module, include_dirs=None):
SourceFile.__init__(self, path=path, module=module, library=library) SourceFile.__init__(self, path=path, module=module)
from .vlog_parser import VerilogParser
self.include_dirs = include_dirs[:] if include_dirs else [] self.include_dirs = include_dirs[:] if include_dirs else []
self.include_dirs.append(path_mod.relpath(self.dirname)) self.include_dirs.append(path_mod.relpath(self.dirname))
def parse(self, graph):
from .vlog_parser import VerilogParser
self.parser = VerilogParser() self.parser = VerilogParser()
self.parser.parse(self, graph)
class SVFile(VerilogFile): class SVFile(VerilogFile):
...@@ -124,7 +133,7 @@ class XCOFile(File): ...@@ -124,7 +133,7 @@ class XCOFile(File):
pass pass
class NGCFile(File): class NGCFile(ManualFile):
"""Xilinx Generated Netlist File""" """Xilinx Generated Netlist File"""
pass pass
...@@ -151,13 +160,11 @@ class MIFFile(File): ...@@ -151,13 +160,11 @@ class MIFFile(File):
class RAMFile(File): class RAMFile(File):
"""Xilinx RAM File""" """Xilinx RAM File"""
pass pass
class HEXFile(SourceFile): class HEXFile(SourceFile):
"""Memory initialization binary file in .hex format""" """Memory initialization binary file in .hex format"""
pass pass
...@@ -179,19 +186,19 @@ class VEOFile(File): ...@@ -179,19 +186,19 @@ class VEOFile(File):
class XCIFile(SourceFile): class XCIFile(SourceFile):
"""Xilinx Core IP File""" """Xilinx Core IP File"""
def __init__(self, path, module, library=None): def parse(self, graph):
SourceFile.__init__(self, path=path, module=module, library=library)
from .xci_parser import XCIParser from .xci_parser import XCIParser
self.parser = XCIParser() self.parser = XCIParser()
self.parser.parse(self, graph)
class BDFile(SourceFile): class BDFile(SourceFile):
"""Xilinx Block Design""" """Xilinx Block Design"""
def __init__(self, path, module, library=None): def parse(self, graph):
SourceFile.__init__(self, path=path, module=module, library=library)
from .bd_parser import BDParser from .bd_parser import BDParser
self.parser = BDParser() self.parser = BDParser()
self.parser.parse(self, graph)
XILINX_FILE_DICT = { XILINX_FILE_DICT = {
...@@ -384,7 +391,7 @@ SV_EXTENSIONS = ( ...@@ -384,7 +391,7 @@ SV_EXTENSIONS = (
'svh') 'svh')
def create_source_file(path, module, library=None, include_dirs=None): def create_source_file(path, module, include_dirs=None):
"""Function that analyzes the given arguments and returns a new HDL source """Function that analyzes the given arguments and returns a new HDL source
file of the appropriated type""" file of the appropriated type"""
assert path assert path
...@@ -395,19 +402,20 @@ def create_source_file(path, module, library=None, include_dirs=None): ...@@ -395,19 +402,20 @@ def create_source_file(path, module, library=None, include_dirs=None):
extension = extension[1:] extension = extension[1:]
logging.debug("add file " + path) logging.debug("add file " + path)
if extension in VHDL_EXTENSIONS: if extension in ("ngc", ):
logging.warning("file %s in %s has no explicit provided units, rewrite as '(filename, unit)'",
path, module)
new_file = File(path=path, module=module)
elif extension in VHDL_EXTENSIONS:
new_file = VHDLFile(path=path, new_file = VHDLFile(path=path,
module=module, module=module)
library=library)
elif extension in VERILOG_EXTENSIONS: elif extension in VERILOG_EXTENSIONS:
new_file = VerilogFile(path=path, new_file = VerilogFile(path=path,
module=module, module=module,
library=library,
include_dirs=include_dirs) include_dirs=include_dirs)
elif extension in SV_EXTENSIONS: elif extension in SV_EXTENSIONS:
new_file = SVFile(path=path, new_file = SVFile(path=path,
module=module, module=module,
library=library,
include_dirs=include_dirs) include_dirs=include_dirs)
elif extension == 'wb': elif extension == 'wb':
new_file = WBGenFile(path=path, module=module) new_file = WBGenFile(path=path, module=module)
...@@ -416,9 +424,9 @@ def create_source_file(path, module, library=None, include_dirs=None): ...@@ -416,9 +424,9 @@ def create_source_file(path, module, library=None, include_dirs=None):
elif extension == 'sdc': elif extension == 'sdc':
new_file = SDCFile(path=path, module=module) new_file = SDCFile(path=path, module=module)
elif extension == 'xci': elif extension == 'xci':
new_file = XCIFile(path=path, module=module, library=library) new_file = XCIFile(path=path, module=module)
elif extension == 'cxf': elif extension == 'cxf':
new_file = CXFFile(path=path, module=module, library=library) new_file = CXFFile(path=path, module=module)
elif extension in XILINX_FILE_DICT: elif extension in XILINX_FILE_DICT:
new_file = XILINX_FILE_DICT[extension](path=path, module=module) new_file = XILINX_FILE_DICT[extension](path=path, module=module)
elif extension in ALTERA_FILE_DICT: elif extension in ALTERA_FILE_DICT:
...@@ -430,3 +438,19 @@ def create_source_file(path, module, library=None, include_dirs=None): ...@@ -430,3 +438,19 @@ def create_source_file(path, module, library=None, include_dirs=None):
else: else:
raise Exception("Unknown extension '{}' for file {}".format(extension, path)) raise Exception("Unknown extension '{}' for file {}".format(extension, path))
return new_file return new_file
def create_source_file_with_deps(path, module, provide, depends):
"""Function that analyzes the given arguments and returns a new HDL source
file of the appropriated type"""
assert path
assert os.path.isabs(path)
_, extension = os.path.splitext(path)
assert extension[0] == '.'
# Remove '.'
extension = extension[1:]
logging.debug("add file with deps) " + path)
if extension == 'ngc':
return NGCFile(path, module, provide, depends)
raise Exception("Unknown extension '{}' for file {} (with deps)".format(extension, path))
hdlmake/tools/ise.py
View file @ 0383ad54
...@@ -78,7 +78,8 @@ class ToolISE(MakefileSyn): ...@@ -78,7 +78,8 @@ class ToolISE(MakefileSyn):
HDL_FILES = { HDL_FILES = {
VHDLFile: 'HDL_FILES[VHDLFile] - NEEDS SETTING!!!', VHDLFile: 'HDL_FILES[VHDLFile] - NEEDS SETTING!!!',
VerilogFile: _ISE_ADD_SRCFILE, VerilogFile: _ISE_ADD_SRCFILE,
SVFile: _ISE_ADD_SRCFILE} SVFile: _ISE_ADD_SRCFILE,
NGCFile: None}
......
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