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Hdlmake
Commit 18f7e682 authored by Benny Simonsen's avatar Benny Simonsen
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Merge branch 'develop' into develop-specify_top_library

parents 2a98971e b1c7ba85
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Showing with 9 additions and 4 deletions
hdlmake/tools/vivado_sim.py
View file @ 18f7e682
......@@ -50,7 +50,7 @@ class ToolVivadoSim(ToolXilinxProject, MakefileSim):
'mrproper': ["*.wdb", "*.vcd"]}
SIMULATOR_CONTROLS = {'vlog': 'xvlog $<',
'vhdl': 'xvhdl $<',
'vhdl': 'xvhdl --work {work} $<',
'compiler': 'xelab -debug all $(TOP_MODULE) '
'-s $(TOP_MODULE)'}
......@@ -71,6 +71,8 @@ class ToolVivadoSim(ToolXilinxProject, MakefileSim):
def _makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for Vivado Simulator"""
libs = self.get_all_libs()
self._makefile_sim_libs_variables(libs)
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + self.SIMULATOR_CONTROLS['compiler'])
self.writeln()
......
testsuite/019vsim/Makefile.ref
View file @ 18f7e682
......@@ -14,11 +14,14 @@ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
LIBS := work
LIB_IND := work/.work
simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
xelab -debug all $(TOP_MODULE) -s $(TOP_MODULE)
work/gate/.gate_vhdl: ../files/gate.vhdl
xvhdl $<
xvhdl --work work $<
@mkdir -p $(dir $@) && touch $@
......
testsuite/test_all.py
View file @ 18f7e682
......@@ -190,10 +190,10 @@ def test_riviera017():
def test_vivado018():
run_compare(path="018vivado")
def test_vivado_props():
def test_vivado_props054():
run_compare(path="054vivado_props")
def test_vivado_sim():
def test_vivado_sim019():
run_compare(path="019vsim")
def test_git_fetch():
......
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