Skip to content

H
Hdlmake
Commit b1c7ba85 authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

testsuite: adjust baseline for 019vsim

parent e21f2439
Hide whitespace changes
Inline Side-by-side
Showing with 6 additions and 3 deletions
testsuite/019vsim/Makefile.ref
View file @ b1c7ba85
......@@ -14,11 +14,14 @@ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
LIBS := work
LIB_IND := work/.work
simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
xelab -debug all $(TOP_MODULE) -s $(TOP_MODULE)
work/gate/.gate_vhdl: ../files/gate.vhdl
xvhdl $<
xvhdl --work work $<
@mkdir -p $(dir $@) && touch $@
......
testsuite/test_all.py
View file @ b1c7ba85
......@@ -190,10 +190,10 @@ def test_riviera017():
def test_vivado018():
run_compare(path="018vivado")
def test_vivado_props():
def test_vivado_props054():
run_compare(path="054vivado_props")
def test_vivado_sim():
def test_vivado_sim019():
run_compare(path="019vsim")
def test_git_fetch():
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment