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Hdlmake
Commits
19aa25c2
Commit
19aa25c2
authored
Aug 04, 2016
by
Javier D. Garcia-Lasheras
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Plain Diff
Create a new Class to contain common Xilinx stuff
parent
61f439f5
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4 changed files
with
110 additions
and
88 deletions
+110
-88
__init__.py
hdlmake/tools/__init__.py
+1
-0
planahead.py
hdlmake/tools/planahead.py
+3
-42
vivado.py
hdlmake/tools/vivado.py
+2
-46
xilinx.py
hdlmake/tools/xilinx.py
+104
-0
No files found.
hdlmake/tools/__init__.py
View file @
19aa25c2
...
@@ -6,6 +6,7 @@ from .riviera import ToolRiviera
...
@@ -6,6 +6,7 @@ from .riviera import ToolRiviera
from
.ghdl
import
ToolGHDL
from
.ghdl
import
ToolGHDL
from
.sim_makefile_support
import
VsimMakefileWriter
from
.sim_makefile_support
import
VsimMakefileWriter
from
.xilinx
import
ToolXilinx
from
.ise
import
ToolISE
from
.ise
import
ToolISE
from
.planahead
import
ToolPlanAhead
from
.planahead
import
ToolPlanAhead
from
.vivado
import
ToolVivado
from
.vivado
import
ToolVivado
...
...
hdlmake/tools/planahead.py
View file @
19aa25c2
...
@@ -23,15 +23,15 @@
...
@@ -23,15 +23,15 @@
"""Module providing support for Xilinx PlanAhead synthesis"""
"""Module providing support for Xilinx PlanAhead synthesis"""
from
hdlmake.action
import
ActionMakefile
from
.xilinx
import
ToolXilinx
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
TCLFile
,
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
)
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
)
PLANAHEAD_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
PLANAHEAD_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
class
ToolPlanAhead
(
ActionMakefile
):
class
ToolPlanAhead
(
ToolXilinx
):
"""Class providing the interface for Xilinx PlanAhead synthesis"""
"""Class providing the interface for Xilinx PlanAhead synthesis"""
...
@@ -72,42 +72,3 @@ class ToolPlanAhead(ActionMakefile):
...
@@ -72,42 +72,3 @@ class ToolPlanAhead(ActionMakefile):
"""Get the Xilinx PlanAhead program version"""
"""Get the Xilinx PlanAhead program version"""
return
'unknown'
return
'unknown'
def
makefile_syn_tcl
(
self
,
top_module
,
tcl_controls
):
"""Create a Xilinx PlanAhead project"""
tmp
=
"set_property {0} {1} [{2}]"
syn_device
=
top_module
.
manifest_dict
[
"syn_device"
]
syn_grade
=
top_module
.
manifest_dict
[
"syn_grade"
]
syn_package
=
top_module
.
manifest_dict
[
"syn_package"
]
syn_top
=
top_module
.
manifest_dict
[
"syn_top"
]
create_new
=
[]
create_new
.
append
(
tcl_controls
[
"create"
])
properties
=
[
[
'part'
,
syn_device
+
syn_package
+
syn_grade
,
'current_project'
],
[
'target_language'
,
'VHDL'
,
'current_project'
],
[
'top'
,
syn_top
,
'get_property srcset [current_run]'
]]
for
prop
in
properties
:
create_new
.
append
(
tmp
.
format
(
prop
[
0
],
prop
[
1
],
prop
[
2
]))
tcl_controls
[
"create"
]
=
"
\n
"
.
join
(
create_new
)
super
(
ToolPlanAhead
,
self
)
.
makefile_syn_tcl
(
top_module
,
tcl_controls
)
def
makefile_syn_files
(
self
,
fileset
):
"""Create a Xilinx PlanAhead project"""
self
.
writeln
(
"define TCL_FILES"
)
tmp
=
"add_files -norecurse {0}"
for
file_aux
in
fileset
:
if
(
isinstance
(
file_aux
,
VHDLFile
)
or
isinstance
(
file_aux
,
VerilogFile
)
or
isinstance
(
file_aux
,
SVFile
)
or
isinstance
(
file_aux
,
UCFFile
)
or
isinstance
(
file_aux
,
NGCFile
)
or
isinstance
(
file_aux
,
XMPFile
)
or
isinstance
(
file_aux
,
XCOFile
)):
line
=
tmp
.
format
(
file_aux
.
rel_path
())
else
:
continue
self
.
writeln
(
line
)
self
.
writeln
(
'update_compile_order -fileset sources_1'
)
self
.
writeln
(
'update_compile_order -fileset sim_1'
)
self
.
writeln
(
"endef"
)
self
.
writeln
(
"export TCL_FILES"
)
hdlmake/tools/vivado.py
View file @
19aa25c2
...
@@ -29,7 +29,7 @@ import os
...
@@ -29,7 +29,7 @@ import os
import
string
import
string
import
logging
import
logging
from
hdlmake.action
import
ActionMakefile
from
.xilinx
import
ToolXilinx
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
,
BDFile
,
TCLFile
)
NGCFile
,
XMPFile
,
XCOFile
,
BDFile
,
TCLFile
)
...
@@ -37,7 +37,7 @@ from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, UCFFile,
...
@@ -37,7 +37,7 @@ from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, UCFFile,
VIVADO_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
VIVADO_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
class
ToolVivado
(
ActionMakefile
):
class
ToolVivado
(
ToolXilinx
):
"""Class providing the interface for Xilinx Vivado synthesis"""
"""Class providing the interface for Xilinx Vivado synthesis"""
...
@@ -81,47 +81,3 @@ class ToolVivado(ActionMakefile):
...
@@ -81,47 +81,3 @@ class ToolVivado(ActionMakefile):
"""Get version from Xilinx Vivado binary program"""
"""Get version from Xilinx Vivado binary program"""
return
'unknown'
return
'unknown'
def
makefile_syn_tcl
(
self
,
top_module
,
tcl_controls
):
"""Create a Xilinx Vivado project"""
tmp
=
"set_property {0} {1} [{2}]"
syn_device
=
top_module
.
manifest_dict
[
"syn_device"
]
syn_grade
=
top_module
.
manifest_dict
[
"syn_grade"
]
syn_package
=
top_module
.
manifest_dict
[
"syn_package"
]
syn_top
=
top_module
.
manifest_dict
[
"syn_top"
]
create_new
=
[]
create_new
.
append
(
tcl_controls
[
"create"
])
properties
=
[
[
'part'
,
syn_device
+
syn_package
+
syn_grade
,
'current_project'
],
[
'target_language'
,
'VHDL'
,
'current_project'
],
[
'top'
,
syn_top
,
'get_property srcset [current_run]'
]]
for
prop
in
properties
:
create_new
.
append
(
tmp
.
format
(
prop
[
0
],
prop
[
1
],
prop
[
2
]))
tcl_controls
[
"create"
]
=
"
\n
"
.
join
(
create_new
)
super
(
ToolVivado
,
self
)
.
makefile_syn_tcl
(
top_module
,
tcl_controls
)
def
makefile_syn_files
(
self
,
fileset
):
"""Create a Xilinx Vivado project"""
self
.
writeln
(
"define TCL_FILES"
)
tmp
=
"add_files -norecurse {0}"
tcl
=
"source {0}"
for
file_aux
in
fileset
:
if
(
isinstance
(
file_aux
,
VHDLFile
)
or
isinstance
(
file_aux
,
VerilogFile
)
or
isinstance
(
file_aux
,
SVFile
)
or
isinstance
(
file_aux
,
UCFFile
)
or
isinstance
(
file_aux
,
NGCFile
)
or
isinstance
(
file_aux
,
XMPFile
)
or
isinstance
(
file_aux
,
XCOFile
)
or
isinstance
(
file_aux
,
BDFile
)):
line
=
tmp
.
format
(
file_aux
.
rel_path
())
elif
isinstance
(
file_aux
,
TCLFile
):
line
=
tcl
.
format
(
file_aux
.
rel_path
())
else
:
continue
self
.
writeln
(
line
)
self
.
writeln
(
'update_compile_order -fileset sources_1'
)
self
.
writeln
(
'update_compile_order -fileset sim_1'
)
self
.
writeln
(
"endef"
)
self
.
writeln
(
"export TCL_FILES"
)
hdlmake/tools/xilinx.py
0 → 100644
View file @
19aa25c2
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake. If not, see <http://www.gnu.org/licenses/>.
#
"""Module providing generic support for Xilinx synthesis tools"""
import
subprocess
import
sys
import
os
import
string
import
logging
from
hdlmake.action
import
ActionMakefile
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
NGCFile
,
XMPFile
,
XCOFile
,
BDFile
,
TCLFile
)
VIVADO_STANDARD_LIBS
=
[
'ieee'
,
'std'
]
class
ToolXilinx
(
ActionMakefile
):
"""Class providing the interface for Xilinx Vivado synthesis"""
HDL_FILES
=
[
VHDLFile
,
VerilogFile
,
SVFile
]
TCL_CONTROLS
=
{
'create'
:
'create_project $(PROJECT) ./'
,
'open'
:
'open_project $(PROJECT_FILE)'
,
'save'
:
''
,
'close'
:
'exit'
,
'synthesize'
:
'reset_run synth_1
\n
'
'launch_runs synth_1
\n
'
'wait_on_run synth_1'
,
'translate'
:
''
,
'map'
:
''
,
'par'
:
'reset_run impl_1
\n
'
'launch_runs impl_1
\n
'
'wait_on_run impl_1'
,
'bitstream'
:
'launch_runs impl_1 -to_step write_bitstream
\n
'
'wait_on_run impl_1'
,
'install_source'
:
'$(PROJECT).runs/impl_1/$(SYN_TOP).bit'
}
def
__init__
(
self
):
super
(
ToolXilinx
,
self
)
.
__init__
()
def
detect_version
(
self
,
path
):
"""Get version from Xilinx Vivado binary program"""
return
'unknown'
def
makefile_syn_tcl
(
self
,
top_module
,
tcl_controls
):
"""Create a Xilinx synthesis project by TCL"""
tmp
=
"set_property {0} {1} [{2}]"
syn_device
=
top_module
.
manifest_dict
[
"syn_device"
]
syn_grade
=
top_module
.
manifest_dict
[
"syn_grade"
]
syn_package
=
top_module
.
manifest_dict
[
"syn_package"
]
syn_top
=
top_module
.
manifest_dict
[
"syn_top"
]
create_new
=
[]
create_new
.
append
(
tcl_controls
[
"create"
])
properties
=
[
[
'part'
,
syn_device
+
syn_package
+
syn_grade
,
'current_project'
],
[
'target_language'
,
'VHDL'
,
'current_project'
],
[
'top'
,
syn_top
,
'get_property srcset [current_run]'
]]
for
prop
in
properties
:
create_new
.
append
(
tmp
.
format
(
prop
[
0
],
prop
[
1
],
prop
[
2
]))
tcl_controls
[
"create"
]
=
"
\n
"
.
join
(
create_new
)
super
(
ToolXilinx
,
self
)
.
makefile_syn_tcl
(
top_module
,
tcl_controls
)
def
makefile_syn_files
(
self
,
fileset
):
"""Write the files TCL section of the Makefile"""
self
.
writeln
(
"define TCL_FILES"
)
tmp
=
"add_files -norecurse {0}"
tcl
=
"source {0}"
for
file_aux
in
fileset
:
if
isinstance
(
file_aux
,
TCLFile
):
line
=
tcl
.
format
(
file_aux
.
rel_path
())
else
:
line
=
tmp
.
format
(
file_aux
.
rel_path
())
self
.
writeln
(
line
)
self
.
writeln
(
'update_compile_order -fileset sources_1'
)
self
.
writeln
(
'update_compile_order -fileset sim_1'
)
self
.
writeln
(
"endef"
)
self
.
writeln
(
"export TCL_FILES"
)
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