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Hdlmake
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1dd1da5f
Commit
1dd1da5f
authored
Aug 01, 2019
by
William Kamp
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Upgrade unfetched module from debug to warning.
parent
3ca3557f
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2 changed files
with
2 additions
and
2 deletions
+2
-2
dep_file.py
hdlmake/dep_file.py
+1
-1
core.py
hdlmake/module/core.py
+1
-1
No files found.
hdlmake/dep_file.py
View file @
1dd1da5f
...
...
@@ -63,7 +63,7 @@ class DepRelation(object):
self
.
direction
==
DepRelation
.
USE
):
return
False
if
rel_b
.
rel_type
==
DepRelation
.
MODULE
and
rel_b
.
obj_name
.
startswith
(
"verilog_inst."
):
# ignore relations where verilog instanciates vhdl or IP modules.
# ignore
library in
relations where verilog instanciates vhdl or IP modules.
self_obj_name
=
self
.
obj_name
.
split
(
"."
)[
-
1
]
rel_b_obj_name
=
rel_b
.
obj_name
.
split
(
"."
)[
-
1
]
else
:
...
...
hdlmake/module/core.py
View file @
1dd1da5f
...
...
@@ -70,7 +70,7 @@ class ModuleConfig(object):
else
:
self
.
path
=
path
self
.
isfetched
=
False
logging
.
debu
g
(
"Module
%
s (parent:
%
s) is NOT fetched."
,
logging
.
warnin
g
(
"Module
%
s (parent:
%
s) is NOT fetched."
,
url
,
self
.
parent
.
path
)
else
:
self
.
url
,
self
.
branch
,
self
.
revision
=
url
,
None
,
None
...
...
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