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Hdlmake
Commit 1dd1da5f authored by William Kamp's avatar William Kamp
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Upgrade unfetched module from debug to warning.

parent 3ca3557f
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Showing with 2 additions and 2 deletions
hdlmake/dep_file.py
View file @ 1dd1da5f
...@@ -63,7 +63,7 @@ class DepRelation(object): ...@@ -63,7 +63,7 @@ class DepRelation(object):
self.direction == DepRelation.USE): self.direction == DepRelation.USE):
return False return False
if rel_b.rel_type == DepRelation.MODULE and rel_b.obj_name.startswith("verilog_inst."): if rel_b.rel_type == DepRelation.MODULE and rel_b.obj_name.startswith("verilog_inst."):
# ignore relations where verilog instanciates vhdl or IP modules. # ignore library in relations where verilog instanciates vhdl or IP modules.
self_obj_name = self.obj_name.split(".")[-1] self_obj_name = self.obj_name.split(".")[-1]
rel_b_obj_name = rel_b.obj_name.split(".")[-1] rel_b_obj_name = rel_b.obj_name.split(".")[-1]
else: else:
......
hdlmake/module/core.py
View file @ 1dd1da5f
...@@ -70,7 +70,7 @@ class ModuleConfig(object): ...@@ -70,7 +70,7 @@ class ModuleConfig(object):
else: else:
self.path = path self.path = path
self.isfetched = False self.isfetched = False
logging.debug("Module %s (parent: %s) is NOT fetched.", logging.warning("Module %s (parent: %s) is NOT fetched.",
url, self.parent.path) url, self.parent.path)
else: else:
self.url, self.branch, self.revision = url, None, None self.url, self.branch, self.revision = url, None, None
......
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