Merge branch 'nvc-support' into 'develop'

Add support to NVC simulator See merge request !27

Merge branch 'nvc-support' into 'develop'
Add support to NVC simulator See merge request !27
24aa6947 · Tristan Gingold · f41e6a57 · 0f094cc6 · 24aa6947 · 24aa6947
Commit 24aa6947 authored Jan 17, 2024 by Tristan Gingold
Showing with 133 additions and 0 deletions

load_tool.py hdlmake/tools/load_tool.py +2 -0

nvc.py hdlmake/tools/nvc.py +70 -0

Makefile.ref testsuite/128nvc/Makefile.ref +53 -0

Manifest.py testsuite/128nvc/Manifest.py +8 -0

No files found.
--- a/hdlmake/tools/load_tool.py
+++ b/hdlmake/tools/load_tool.py
@@ -41,6 +41,7 @@ def load_sim_tool(tool_name):
    from .active_hdl import ToolActiveHDL
    from .riviera import ToolRiviera
    from .ghdl import ToolGHDL
+    from .nvc import ToolNVC
    from .vivado_sim import ToolVivadoSim
    available_tools = {'iverilog': ToolIVerilog,
                       'isim': ToolISim,
@@ -48,6 +49,7 @@ def load_sim_tool(tool_name):
                       'active_hdl': ToolActiveHDL,
                       'riviera':  ToolRiviera,
                       'ghdl': ToolGHDL,
+                       'nvc': ToolNVC,
                       'vivado_sim': ToolVivadoSim}
    if tool_name in available_tools:
        logging.debug("Simulation tool to be used found: %s", tool_name)

--- a/hdlmake/tools/nvc.py
+++ b/hdlmake/tools/nvc.py
+#!/usr/bin/python
+# -*- coding: utf-8 -*-
+#
+# Copyright (c) 2013 - 2015 CERN, 2023 CNPEM
+# Authors: Pawel Szostek (pawel.szostek@cern.ch), Augusto Fraga Giachero (augusto.fraga@lnls.br)
+# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
+#
+# This file is part of Hdlmake.
+#
+# Hdlmake is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# Hdlmake is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with Hdlmake.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+"""Module providing support for NVC simulator"""
+
+from __future__ import absolute_import
+import string
+
+from .makefilesim import MakefileSim
+from ..sourcefiles.srcfile import VHDLFile
+
+
+class ToolNVC(MakefileSim):
+
+    """Class providing the interface for NVC simulator"""
+
+    TOOL_INFO = {
+        'name': 'NVC',
+        'id': 'nvc',
+        'windows_bin': 'nvc',
+        'linux_bin': 'nvc'}
+
+    STANDARD_LIBS = ['ieee', 'std']
+
+    HDL_FILES = {VHDLFile: ''}
+
+    CLEAN_TARGETS = {'clean': ["*.cf", "*.o", "$(TOP_MODULE)", "work"],
+                     'mrproper': ["*.vcd"]}
+
+    SIMULATOR_CONTROLS = {'vlog': None,
+                          'vhdl': '$(NVC) --work={work} $(NVC_OPT) -a  $<',
+                          'compiler': '$(NVC) $(NVC_OPT) -e $(TOP_MODULE)'}
+
+    def __init__(self):
+        super(ToolNVC, self).__init__()
+
+    def _makefile_sim_options(self):
+        """Print the NVC options to the Makefile"""
+        self.writeln("NVC := nvc")
+        nvc_opt = self.manifest_dict.get("nvc_opt", '')
+        self.writeln("NVC_OPT := {nvc_opt}\n".format(nvc_opt=nvc_opt))
+
+    def _makefile_sim_compilation(self):
+        """Print the NVC simulation compilation target"""
+        libs = self.get_all_libs()
+        self._makefile_sim_libs_variables(libs)
+        self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
+        self.writeln("\t\t" + self.SIMULATOR_CONTROLS['compiler'])
+        self.writeln('\n')
+        self._makefile_sim_dep_files()
--- a/testsuite/128nvc/Makefile.ref
+++ b/testsuite/128nvc/Makefile.ref
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+TOP_MODULE := gate3
+
+NVC := nvc
+NVC_OPT := --std=2008
+
+#target for performing local simulation
+local: sim_pre_cmd simulation sim_post_cmd
+
+VERILOG_SRC := 
+VERILOG_OBJ := 
+VHDL_SRC := ../files/gate.vhdl \
+../files/gate3.vhd \
+
+VHDL_OBJ := work/gate/.gate_vhdl \
+work/gate3/.gate3_vhd \
+
+LIBS := work
+LIB_IND := work/.work
+
+simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
+		$(NVC) $(NVC_OPT) -e $(TOP_MODULE)
+
+
+work/gate/.gate_vhdl: ../files/gate.vhdl
+		$(NVC) --work=work $(NVC_OPT) -a  $<
+		@mkdir -p $(dir $@) && touch $@
+
+
+work/gate3/.gate3_vhd: ../files/gate3.vhd \
+work/gate/.gate_vhdl
+		$(NVC) --work=work $(NVC_OPT) -a  $<
+		@mkdir -p $(dir $@) && touch $@
+
+
+# USER SIM COMMANDS
+sim_pre_cmd:
+		
+sim_post_cmd:
+		
+
+CLEAN_TARGETS := $(LIBS) *.cf *.o $(TOP_MODULE) work
+
+clean:
+		rm -rf $(CLEAN_TARGETS)
+mrproper: clean
+		rm -rf *.vcd
+
+.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
--- a/testsuite/128nvc/Manifest.py
+++ b/testsuite/128nvc/Manifest.py
+action = "simulation"
+
+sim_tool="nvc"
+nvc_opt="--std=2008"
+
+top_module = "gate3"
+
+files = [ "../files/gate3.vhd", "../files/gate.vhdl" ]