testsuite: adjust baseline

f41e6a57 · Tristan Gingold · db5e2460 · f41e6a57 · f41e6a57 · f41e6a57
Commit f41e6a57 authored Sep 14, 2023 by Tristan Gingold
4 changed files
--- a/testsuite/125arch_in_separate_file/Makefile.ref
+++ b/testsuite/125arch_in_separate_file/Makefile.ref
@@ -48,8 +48,7 @@ work/hdlmake/gate4_e_vhdl
 		vcom $(VCOM_FLAGS) -work work $< 
 		@touch $@

-work/hdlmake/gate4_e_vhdl: ../files/gate4_e.vhdl \
-work/hdlmake/gate4_a_vhdl
+work/hdlmake/gate4_e_vhdl: ../files/gate4_e.vhdl
 		vcom $(VCOM_FLAGS) -work work $< 
 		@touch $@


--- a/testsuite/126package_body_in_separate_file/Makefile.ref
+++ b/testsuite/126package_body_in_separate_file/Makefile.ref
@@ -43,8 +43,7 @@ work/hdlmake/pkg5_vhdl
 		vcom $(VCOM_FLAGS) -work work $< 
 		@touch $@

-work/hdlmake/pkg5_vhdl: ../files/pkg5.vhdl \
-work/hdlmake/pkg5_body_vhdl
+work/hdlmake/pkg5_vhdl: ../files/pkg5.vhdl
 		vcom $(VCOM_FLAGS) -work work $< 
 		@touch $@


--- a/testsuite/127arch_in_separate_file/Makefile.ref
+++ b/testsuite/127arch_in_separate_file/Makefile.ref
@@ -17,12 +17,12 @@ local: sim_pre_cmd simulation sim_post_cmd
 VERILOG_SRC := 
 VERILOG_OBJ := 
 VHDL_SRC := ../files/gate.vhdl \
-../files/gate4_x_a.vhdl \
 ../files/gate4_e.vhdl \
+../files/gate4_x_a.vhdl \

 VHDL_OBJ := work/hdlmake/gate_vhdl \
-work/hdlmake/gate4_x_a_vhdl \
 work/hdlmake/gate4_e_vhdl \
+work/hdlmake/gate4_x_a_vhdl \

 INCLUDE_DIRS :=
 LIBS := work
@@ -42,14 +42,13 @@ work/hdlmake/gate_vhdl: ../files/gate.vhdl
 		vcom $(VCOM_FLAGS) -work work $< 
 		@touch $@

-work/hdlmake/gate4_x_a_vhdl: ../files/gate4_x_a.vhdl \
-work/hdlmake/gate_vhdl \
-work/hdlmake/gate4_e_vhdl
+work/hdlmake/gate4_e_vhdl: ../files/gate4_e.vhdl
 		vcom $(VCOM_FLAGS) -work work $< 
 		@touch $@

-work/hdlmake/gate4_e_vhdl: ../files/gate4_e.vhdl \
-work/hdlmake/gate4_x_a_vhdl
+work/hdlmake/gate4_x_a_vhdl: ../files/gate4_x_a.vhdl \
+work/hdlmake/gate_vhdl \
+work/hdlmake/gate4_e_vhdl
 		vcom $(VCOM_FLAGS) -work work $< 
 		@touch $@


--- a/testsuite/test_all.py
+++ b/testsuite/test_all.py
@@ -600,6 +600,9 @@ def test_arch_in_separate_file_125():
 def test_package_body_in_separate_file_126():
    run_compare(path="126package_body_in_separate_file")

+def test_arch_in_separate_file_127():
+    run_compare(path="127arch_in_separate_file")
+
 @pytest.mark.xfail
 def test_xfail():
    """This is a self-consistency test: the test is known to fail"""