Commit f41e6a57 authored by Tristan Gingold's avatar Tristan Gingold

testsuite: adjust baseline

parent db5e2460
...@@ -48,8 +48,7 @@ work/hdlmake/gate4_e_vhdl ...@@ -48,8 +48,7 @@ work/hdlmake/gate4_e_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@touch $@ @touch $@
work/hdlmake/gate4_e_vhdl: ../files/gate4_e.vhdl \ work/hdlmake/gate4_e_vhdl: ../files/gate4_e.vhdl
work/hdlmake/gate4_a_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@touch $@ @touch $@
......
...@@ -43,8 +43,7 @@ work/hdlmake/pkg5_vhdl ...@@ -43,8 +43,7 @@ work/hdlmake/pkg5_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@touch $@ @touch $@
work/hdlmake/pkg5_vhdl: ../files/pkg5.vhdl \ work/hdlmake/pkg5_vhdl: ../files/pkg5.vhdl
work/hdlmake/pkg5_body_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@touch $@ @touch $@
......
...@@ -17,12 +17,12 @@ local: sim_pre_cmd simulation sim_post_cmd ...@@ -17,12 +17,12 @@ local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
../files/gate4_x_a.vhdl \
../files/gate4_e.vhdl \ ../files/gate4_e.vhdl \
../files/gate4_x_a.vhdl \
VHDL_OBJ := work/hdlmake/gate_vhdl \ VHDL_OBJ := work/hdlmake/gate_vhdl \
work/hdlmake/gate4_x_a_vhdl \
work/hdlmake/gate4_e_vhdl \ work/hdlmake/gate4_e_vhdl \
work/hdlmake/gate4_x_a_vhdl \
INCLUDE_DIRS := INCLUDE_DIRS :=
LIBS := work LIBS := work
...@@ -42,14 +42,13 @@ work/hdlmake/gate_vhdl: ../files/gate.vhdl ...@@ -42,14 +42,13 @@ work/hdlmake/gate_vhdl: ../files/gate.vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@touch $@ @touch $@
work/hdlmake/gate4_x_a_vhdl: ../files/gate4_x_a.vhdl \ work/hdlmake/gate4_e_vhdl: ../files/gate4_e.vhdl
work/hdlmake/gate_vhdl \
work/hdlmake/gate4_e_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@touch $@ @touch $@
work/hdlmake/gate4_e_vhdl: ../files/gate4_e.vhdl \ work/hdlmake/gate4_x_a_vhdl: ../files/gate4_x_a.vhdl \
work/hdlmake/gate4_x_a_vhdl work/hdlmake/gate_vhdl \
work/hdlmake/gate4_e_vhdl
vcom $(VCOM_FLAGS) -work work $< vcom $(VCOM_FLAGS) -work work $<
@touch $@ @touch $@
......
...@@ -600,6 +600,9 @@ def test_arch_in_separate_file_125(): ...@@ -600,6 +600,9 @@ def test_arch_in_separate_file_125():
def test_package_body_in_separate_file_126(): def test_package_body_in_separate_file_126():
run_compare(path="126package_body_in_separate_file") run_compare(path="126package_body_in_separate_file")
def test_arch_in_separate_file_127():
run_compare(path="127arch_in_separate_file")
@pytest.mark.xfail @pytest.mark.xfail
def test_xfail(): def test_xfail():
"""This is a self-consistency test: the test is known to fail""" """This is a self-consistency test: the test is known to fail"""
......
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