Update documentation to reflect support for NVC

Also include a simulation example in tests/counter/sim/nvc.

Update documentation to reflect support for NVC
Also include a simulation example in tests/counter/sim/nvc.
30766011 · Augusto Fraga Giachero · 460f8e1e · 30766011 · 30766011
Commit 30766011 authored Jan 19, 2024 by Augusto Fraga Giachero
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index.rst docs/index.rst +13 -0

Manifest.py tests/counter/sim/nvc/vhdl/Manifest.py +9 -0

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--- a/docs/index.rst
+++ b/docs/index.rst
@@ -131,6 +131,8 @@ Supported Tools
 +--------------------------+-----------+------------+
 | GHDL                     | n.a.      | VHDL       |
 +--------------------------+-----------+------------+
+| NVC                      | n.a.      | VHDL       |
+--------------------------+-----------+------------+

 Supported Operating Systems
 ---------------------------
@@ -1533,6 +1535,17 @@ GHDL specific variables:
 | ghdl_opt       | str          | Additional options for ghdl                                     | ""        |
 +----------------+--------------+-----------------------------------------------------------------+-----------+

+NVC specific variables:
+
+------------------+--------------+-----------------------------------------------------------------+-----------+
+| Name             | Type         | Description                                                     | Default   |
+==================+==============+=================================================================+===========+
+| nvc_opt          | str          | Additional global options for nvc                               | ""        |
+------------------+--------------+-----------------------------------------------------------------+-----------+
+| nvc_analysis_opt | str          | Additional analysis options for nvc                             | ""        |
+------------------+--------------+-----------------------------------------------------------------+-----------+
+| nvc_elab_opt     | str          | Additional elaboration options for nvc                          | ""        |
+------------------+--------------+-----------------------------------------------------------------+-----------+


 Synthesis variables

--- a/tests/counter/sim/nvc/vhdl/Manifest.py
+++ b/tests/counter/sim/nvc/vhdl/Manifest.py
+action = "simulation"
+sim_tool = "nvc"
+sim_top = "counter_tb"
+
+sim_post_cmd = "nvc -r counter_tb --stop-time=6us --format=vcd --wave=counter_tb.vcd"
+
+modules = {
+  "local" : [ "../../../testbench/counter_tb/vhdl" ],
+}