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Commit 30766011 authored by Augusto Fraga Giachero's avatar Augusto Fraga Giachero
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Update documentation to reflect support for NVC 

Also include a simulation example in tests/counter/sim/nvc.
parent 460f8e1e
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docs/index.rst
View file @ 30766011
...@@ -131,6 +131,8 @@ Supported Tools ...@@ -131,6 +131,8 @@ Supported Tools
+--------------------------+-----------+------------+ +--------------------------+-----------+------------+
| GHDL | n.a. | VHDL | | GHDL | n.a. | VHDL |
+--------------------------+-----------+------------+ +--------------------------+-----------+------------+
| NVC | n.a. | VHDL |
+--------------------------+-----------+------------+
Supported Operating Systems Supported Operating Systems
--------------------------- ---------------------------
...@@ -1533,6 +1535,17 @@ GHDL specific variables: ...@@ -1533,6 +1535,17 @@ GHDL specific variables:
| ghdl_opt | str | Additional options for ghdl | "" | | ghdl_opt | str | Additional options for ghdl | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+ +----------------+--------------+-----------------------------------------------------------------+-----------+
NVC specific variables:
+------------------+--------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+==================+==============+=================================================================+===========+
| nvc_opt | str | Additional global options for nvc | "" |
+------------------+--------------+-----------------------------------------------------------------+-----------+
| nvc_analysis_opt | str | Additional analysis options for nvc | "" |
+------------------+--------------+-----------------------------------------------------------------+-----------+
| nvc_elab_opt | str | Additional elaboration options for nvc | "" |
+------------------+--------------+-----------------------------------------------------------------+-----------+
Synthesis variables Synthesis variables
......
tests/counter/sim/nvc/vhdl/Manifest.py 0 → 100644
View file @ 30766011
action = "simulation"
sim_tool = "nvc"
sim_top = "counter_tb"
sim_post_cmd = "nvc -r counter_tb --stop-time=6us --format=vcd --wave=counter_tb.vcd"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
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