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Hdlmake
Commit 33c3e8ea authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Massive hierarchy refactoring on tool info constants

parent ec286e54
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Showing with 168 additions and 147 deletions
hdlmake/action/makefile.py
View file @ 33c3e8ea
......@@ -39,6 +39,11 @@ class ActionMakefile(Action):
def __init__(self, filename=None):
self._file = None
self._initialized = False
self._tool_info = {}
self._clean_targets = {}
self._tcl_controls = {}
self._hdl_files = []
self._supported_files = []
if filename:
self._filename = filename
else:
......@@ -55,20 +60,20 @@ class ActionMakefile(Action):
if os.path.exists(file_aux):
self.write("include %s\n" % file_aux)
def _print_tool_clean(self, clean_targets):
def _print_tool_clean(self):
"""Print the Makefile target for cleaning intermediate files"""
self.writeln("#target for cleaning intermediate files")
self.writeln("clean:")
tmp = "\t\t" + path_mod.del_command() + \
" $(LIBS) " + ' '.join(clean_targets["clean"])
" $(LIBS) " + ' '.join(self._clean_targets["clean"])
self.writeln(tmp)
def _print_tool_mrproper(self, clean_targets):
def _print_tool_mrproper(self):
"""Print the Makefile target for cleaning final files"""
self.writeln("#target for cleaning final files")
self.writeln("mrproper: clean")
tmp = "\t\t" + path_mod.del_command() + \
" " + ' '.join(clean_targets["mrproper"])
" " + ' '.join(self._clean_targets["mrproper"])
self.writeln(tmp)
def initialize(self):
......
hdlmake/action/simulation.py
View file @ 33c3e8ea
......@@ -103,5 +103,5 @@ class ActionSimulation(
tool_object.makefile_sim_sources(dep_files)
tool_object.makefile_sim_compilation(dep_files, top_module)
tool_object.makefile_sim_command(top_module)
tool_object.makefile_sim_clean(tool_object.CLEAN_TARGETS)
tool_object.makefile_sim_clean()
tool_object.makefile_sim_phony(top_module)
hdlmake/action/synthesis.py
View file @ 33c3e8ea
......@@ -226,12 +226,12 @@ end sdb_meta_pkg;""")
module=self.get_module_by_path("."))])
tool_object._print_incl_makefiles(top_module)
tool_object.makefile_syn_top(top_module, tool_path, tool_info)
tool_object.makefile_syn_tcl(top_module, tool_ctrl)
tool_object.makefile_syn_top(top_module, tool_path)
tool_object.makefile_syn_tcl(top_module)
tool_object.makefile_syn_files(fileset)
tool_object.makefile_syn_local()
tool_object.makefile_syn_command(top_module)
tool_object.makefile_syn_build()
tool_object.makefile_syn_clean(tool_object.CLEAN_TARGETS)
tool_object.makefile_syn_clean()
tool_object.makefile_syn_phony()
logging.info(name + " project file generated.")
hdlmake/tools/__init__.py
View file @ 33c3e8ea
"""Package that provides all the tool specific stuff"""
from .iverilog import ToolIVerilog
from .isim import ToolISim
from .modelsim import ToolModelsim
......
hdlmake/tools/active_hdl.py
View file @ 33c3e8ea
......@@ -37,13 +37,16 @@ class ToolActiveHDL(ToolSim):
'windows_bin': 'vsimsa',
'linux_bin': None}
SUPPORTED_FILES = []
HDL_FILES = [VHDLFile, VerilogFile, SVFile]
CLEAN_TARGETS = {'clean': ["run.command", "library.cfg", "work"],
'mrproper': ["*.vcd", "*.asdb"]}
def __init__(self):
super(ToolActiveHDL, self).__init__()
self._tool_info.update(ToolActiveHDL.TOOL_INFO)
self._hdl_files.extend(ToolActiveHDL.HDL_FILES)
self._clean_targets.update(ToolActiveHDL.CLEAN_TARGETS)
def detect_version(self, path):
"""Get the version from the Aldec-HDL binary program"""
......
hdlmake/tools/diamond.py
View file @ 33c3e8ea
......@@ -25,7 +25,7 @@
from .make_syn import ToolSyn
from hdlmake.srcfile import EDFFile, LPFFile
from hdlmake.srcfile import EDFFile, LPFFile, VHDLFile, VerilogFile
DIAMOND_STANDARD_LIBS = ['ieee', 'std']
......@@ -43,6 +43,8 @@ class ToolDiamond(ToolSyn):
SUPPORTED_FILES = [EDFFile, LPFFile]
HDL_FILES = [VHDLFile, VerilogFile]
CLEAN_TARGETS = {'clean': ["*.sty", "$(PROJECT)", "run.tcl"],
'mrproper': ["*.jed"]}
......@@ -62,6 +64,11 @@ class ToolDiamond(ToolSyn):
def __init__(self):
super(ToolDiamond, self).__init__()
self._tool_info.update(ToolDiamond.TOOL_INFO)
self._hdl_files.extend(ToolDiamond.HDL_FILES)
self._supported_files.extend(ToolDiamond.SUPPORTED_FILES)
self._clean_targets.update(ToolDiamond.CLEAN_TARGETS)
self._tcl_controls.update(ToolDiamond.TCL_CONTROLS)
def detect_version(self, path):
"""Get version from the Lattice Diamond program"""
......
hdlmake/tools/ghdl.py
View file @ 33c3e8ea
......@@ -41,13 +41,16 @@ class ToolGHDL(ToolSim):
'windows_bin': 'ghdl',
'linux_bin': 'ghdl'}
SUPPORTED_FILES = []
HDL_FILES = [VHDLFile]
CLEAN_TARGETS = {'clean': ["*.cf", "*.o", "$(TOP_MODULE)"],
'mrproper': ["*.vcd"]}
def __init__(self):
super(ToolGHDL, self).__init__()
self._tool_info.update(ToolGHDL.TOOL_INFO)
self._hdl_files.extend(ToolGHDL.HDL_FILES)
self._clean_targets.update(ToolGHDL.CLEAN_TARGETS)
def detect_version(self, path):
"""Get tool version for GHDL"""
......
hdlmake/tools/ise.py
View file @ 33c3e8ea
......@@ -33,7 +33,8 @@ from subprocess import Popen, PIPE
from .make_syn import ToolSyn
from hdlmake.util import path as path_mod
from hdlmake.srcfile import (UCFFile, CDCFile, NGCFile)
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
UCFFile, CDCFile, NGCFile)
XML_IMPL = xml.dom.minidom.getDOMImplementation()
......@@ -65,6 +66,8 @@ class ToolISE(ToolSyn):
SUPPORTED_FILES = [UCFFile, CDCFile, NGCFile]
HDL_FILES = [VHDLFile, VerilogFile, SVFile]
CLEAN_TARGETS = {'clean': ["xst xlnx_auto_*_xdb", "iseconfig _xmsgs",
"_ngo", "*.b", "*_summary.html", "*.tcl",
"*.bld", "*.cmd_log", "*.drc", "*.lso", "*.ncd",
......@@ -97,6 +100,11 @@ class ToolISE(ToolSyn):
def __init__(self):
super(ToolISE, self).__init__()
self._tool_info.update(ToolISE.TOOL_INFO)
self._hdl_files.extend(ToolISE.HDL_FILES)
self._supported_files.extend(ToolISE.SUPPORTED_FILES)
self._clean_targets.update(ToolISE.CLEAN_TARGETS)
self._tcl_controls.update(ToolISE.TCL_CONTROLS)
def detect_version(self, path):
"""Method returning a string with the Xilinx ISE version from path"""
......@@ -128,7 +136,7 @@ class ToolISE(ToolSyn):
return ise_version
def makefile_syn_tcl(self, top_module, tcl_controls):
def makefile_syn_tcl(self, top_module):
"""Create a Xilinx synthesis project by TCL"""
tmp = "{0}set {1} {2}"
syn_device = top_module.manifest_dict["syn_device"]
......@@ -144,7 +152,7 @@ class ToolISE(ToolSyn):
" and can not be guessed!")
quit(-1)
create_new = []
create_new.append(tcl_controls["create"])
create_new.append(self._tcl_controls["create"])
properties = [
['project ', 'family', syn_family],
['project ', 'device', syn_device],
......@@ -156,8 +164,8 @@ class ToolISE(ToolSyn):
['', 'compile_directory', '.']]
for prop in properties:
create_new.append(tmp.format(prop[0], prop[1], prop[2]))
tcl_controls["create"] = "\n".join(create_new)
super(ToolISE, self).makefile_syn_tcl(top_module, tcl_controls)
self._tcl_controls["create"] = "\n".join(create_new)
super(ToolISE, self).makefile_syn_tcl(top_module)
def makefile_syn_files(self, fileset):
"""Write the files TCL section of the Makefile"""
......
hdlmake/tools/isim.py
View file @ 33c3e8ea
......@@ -53,7 +53,7 @@ class ToolISim(ToolSim):
'windows_bin': 'isimgui',
'linux_bin': 'isimgui'}
SUPPORTED_FILES = []
HDL_FILES = [VerilogFile, VHDLFile]
CLEAN_TARGETS = {'clean': ["./xilinxsim.ini $(LIBS)", "fuse.xmsgs",
"fuse.log", "fuseRelaunch.cmd", "isim",
......@@ -63,6 +63,9 @@ class ToolISim(ToolSim):
def __init__(self):
super(ToolISim, self).__init__()
self._tool_info.update(ToolISim.TOOL_INFO)
self._hdl_files.extend(ToolISim.HDL_FILES)
self._clean_targets.update(ToolISim.CLEAN_TARGETS)
def detect_version(self, path):
"""Get version from Xilinx ISim simulator program"""
......
hdlmake/tools/iverilog.py
View file @ 33c3e8ea
......@@ -48,13 +48,16 @@ class ToolIVerilog(ToolSim):
'windows_bin': 'iverilog',
'linux_bin': 'iverilog'}
SUPPORTED_FILES = []
HDL_FILES = [VerilogFile, VHDLFile, SVFile]
CLEAN_TARGETS = {'clean': ["run.command", "ivl_vhdl_work"],
'mrproper': ["*.vcd", "*.vvp"]}
def __init__(self):
super(ToolIVerilog, self).__init__()
self._tool_info.update(ToolIVerilog.TOOL_INFO)
self._hdl_files.extend(ToolIVerilog.HDL_FILES)
self._clean_targets.update(ToolIVerilog.CLEAN_TARGETS)
def detect_version(self, path):
"""Get version from Icarus Verilog program"""
......
hdlmake/tools/libero.py
View file @ 33c3e8ea
......@@ -44,6 +44,8 @@ class ToolLibero(ToolSyn):
SUPPORTED_FILES = [SDCFile, PDCFile]
HDL_FILES = [VHDLFile, VerilogFile]
CLEAN_TARGETS = {'clean': ["$(PROJECT)", "run.tcl"],
'mrproper': ["*.pdb", "*.stp"]}
......@@ -64,6 +66,11 @@ class ToolLibero(ToolSyn):
def __init__(self):
super(ToolLibero, self).__init__()
self._tool_info.update(ToolLibero.TOOL_INFO)
self._hdl_files.extend(ToolLibero.HDL_FILES)
self._supported_files.extend(ToolLibero.SUPPORTED_FILES)
self._clean_targets.update(ToolLibero.CLEAN_TARGETS)
self._tcl_controls.update(ToolLibero.TCL_CONTROLS)
def detect_version(self, path):
"""Get version for Microsemi Libero IDE synthesis"""
......
hdlmake/tools/make_sim.py
View file @ 33c3e8ea
"""Module providing the synthesis functionality for writing Makefiles"""
"""Module providing the simulation functionality for writing Makefiles"""
import os
import sys
import string
import platform
from hdlmake.action import ActionMakefile
from hdlmake.util import path as path_mod
class ToolSim(ActionMakefile):
......@@ -16,6 +14,7 @@ class ToolSim(ActionMakefile):
super(ToolSim, self).__init__()
def makefile_sim_top(self, top_module):
"""Generic method to write the simulation Makefile top section"""
top_parameter = string.Template("""\
TOP_MODULE := ${top_module}
PWD := $$(shell pwd)
......@@ -24,46 +23,47 @@ PWD := $$(shell pwd)
top_module=top_module.manifest_dict["sim_top"]))
def makefile_sim_options(self, top_module):
"""End stub method to write the synthesis Makefile options section"""
pass
def makefile_sim_local(self, top_module):
"""Generic method to write the simulation Makefile local target"""
self.writeln("#target for performing local simulation\n"
"local: sim_pre_cmd simulation sim_post_cmd\n")
def makefile_sim_sources(self, fileset):
"""Generic method to write the simulation Makefile HDL sources"""
from hdlmake.srcfile import VerilogFile, VHDLFile
self.write("VERILOG_SRC := ")
for vl in fileset.filter(VerilogFile):
self.write(vl.rel_path() + " \\\n")
self.write("\n")
for vlog in fileset.filter(VerilogFile):
self.writeln(vlog.rel_path() + " \\")
self.writeln()
self.write("VERILOG_OBJ := ")
for vl in fileset.filter(VerilogFile):
# make a file compilation indicator (these .dat files are made even if
# the compilation process fails) and add an ending according to file's
# extension (.sv and .vhd files may have the same corename and this
# causes a mess
self.write(
for vlog in fileset.filter(VerilogFile):
# make a file compilation indicator (these .dat files are made even
# if the compilation process fails) and add an ending according
# to file's extension (.sv and .vhd files may have the same
# corename and this causes a mess
self.writeln(
os.path.join(
vl.library,
vl.purename,
vlog.library,
vlog.purename,
"." +
vl.purename +
vlog.purename +
"_" +
vl.extension(
vlog.extension(
)) +
" \\\n")
self.write('\n')
" \\")
self.writeln()
self.write("VHDL_SRC := ")
for vhdl in fileset.filter(VHDLFile):
self.write(vhdl.rel_path() + " \\\n")
self.writeln()
# list vhdl objects (_primary.dat files)
self.write("VHDL_OBJ := ")
for vhdl in fileset.filter(VHDLFile):
# file compilation indicator (important: add _vhd ending)
self.write(
self.writeln(
os.path.join(
vhdl.library,
vhdl.purename,
......@@ -72,20 +72,19 @@ PWD := $$(shell pwd)
"_" +
vhdl.extension(
)) +
" \\\n")
self.write('\n')
" \\")
self.writeln()
def makefile_sim_command(self, top_module):
"""Generic method to write the simulation Makefile user commands"""
if top_module.manifest_dict["sim_pre_cmd"]:
sim_pre_cmd = top_module.manifest_dict["sim_pre_cmd"]
else:
sim_pre_cmd = ''
if top_module.manifest_dict["sim_post_cmd"]:
sim_post_cmd = top_module.manifest_dict["sim_post_cmd"]
else:
sim_post_cmd = ''
sim_command = string.Template("""# USER SIM COMMANDS
sim_pre_cmd:
\t\t${sim_pre_cmd}
......@@ -95,10 +94,10 @@ sim_post_cmd:
self.writeln(sim_command.substitute(sim_pre_cmd=sim_pre_cmd,
sim_post_cmd=sim_post_cmd))
def makefile_sim_clean(self, clean_targets):
"""Print the Makefile clean target for synthesis"""
self._print_tool_clean(clean_targets)
self._print_tool_mrproper(clean_targets)
def makefile_sim_clean(self):
"""Generic method to write the simulation Makefile user clean target"""
self._print_tool_clean()
self._print_tool_mrproper()
def makefile_sim_phony(self, top_module):
"""Print simulation PHONY target list to the Makefile"""
......
hdlmake/tools/make_syn.py
View file @ 33c3e8ea
"""Module providing the synthesis functionality for writing Makefiles"""
import os
import sys
import string
import platform
from hdlmake.action import ActionMakefile
from hdlmake.util import path as path_mod
class ToolSyn(ActionMakefile):
"""Class that provides the Makefile writing methods and status"""
"""Class that provides the synthesis Makefile writing methods and status"""
def __init__(self):
super(ToolSyn, self).__init__()
def makefile_syn_top(self, top_module, tool_path, tool_info):
def makefile_syn_top(self, top_module, tool_path):
"""Create the top part of the synthesis Makefile"""
if path_mod.check_windows():
tcl_interpreter = tool_info["windows_bin"]
tcl_interpreter = self._tool_info["windows_bin"]
else:
tcl_interpreter = tool_info["linux_bin"]
tcl_interpreter = self._tool_info["linux_bin"]
top_parameter = string.Template("""\
TOP_MODULE := ${top_module}
PWD := $$(shell pwd)
......@@ -33,11 +30,11 @@ TCL_INTERPRETER := $$(TOOL_PATH)/${tcl_interpreter}
self.writeln(top_parameter.substitute(
tcl_interpreter=tcl_interpreter,
project_name=top_module.manifest_dict["syn_project"],
project_ext=tool_info["project_ext"],
project_ext=self._tool_info["project_ext"],
tool_path=tool_path,
top_module=top_module.manifest_dict["syn_top"]))
def makefile_syn_tcl(self, top_module, tcl_controls):
def makefile_syn_tcl(self, top_module):
"""Create the Makefile TCL dictionary for the selected tool"""
tcl_string = string.Template("""\
......@@ -88,22 +85,23 @@ export TCL_BITSTREAM
""")
self.writeln(tcl_string.substitute(
tcl_create=tcl_controls["create"],
tcl_open=tcl_controls["open"],
tcl_save=tcl_controls["save"],
tcl_close=tcl_controls["close"],
tcl_synthesize=tcl_controls["synthesize"],
tcl_translate=tcl_controls["translate"],
tcl_map=tcl_controls["map"],
tcl_par=tcl_controls["par"],
tcl_bitstream=tcl_controls["bitstream"]))
tcl_create=self._tcl_controls["create"],
tcl_open=self._tcl_controls["open"],
tcl_save=self._tcl_controls["save"],
tcl_close=self._tcl_controls["close"],
tcl_synthesize=self._tcl_controls["synthesize"],
tcl_translate=self._tcl_controls["translate"],
tcl_map=self._tcl_controls["map"],
tcl_par=self._tcl_controls["par"],
tcl_bitstream=self._tcl_controls["bitstream"]))
def makefile_syn_local(self):
"""Generic method to write the synthesis Makefile local target"""
self.writeln("#target for performing local synthesis\n"
"local: syn_pre_cmd synthesis syn_post_cmd\n")
def makefile_syn_build(self):
"""Generate a Makefile to handle a synthesis project"""
"""Generate the synthesis Makefile targets for handling design build"""
self.writeln("""\
#target for performing local synthesis
synthesis: bitstream
......@@ -213,14 +211,14 @@ syn_post_bitstream_cmd:
syn_post_bitstream_cmd=top_module.manifest_dict[
"syn_post_bitstream_cmd"]))
def makefile_syn_clean(self, clean_targets):
def makefile_syn_clean(self):
"""Print the Makefile clean target for synthesis"""
self._print_tool_clean(clean_targets)
self._print_tool_clean()
self.writeln("\t\t" + path_mod.del_command() +
" synthesize translate map par bitstream")
self.writeln("\t\t" + path_mod.del_command() +
" tcl_synthesize tcl_translate tcl_map tcl_par tcl_bitstream")
self._print_tool_mrproper(clean_targets)
self._print_tool_mrproper()
def makefile_syn_phony(self):
"""Print synthesis PHONY target list to the Makefile"""
......
hdlmake/tools/modelsim.py
View file @ 33c3e8ea
......@@ -41,8 +41,6 @@ class ToolModelsim(VsimMakefileWriter):
'windows_bin': 'vsim',
'linux_bin': 'vsim'}
SUPPORTED_FILES = []
CLEAN_TARGETS = {'clean': ["./modelsim.ini", "transcript"],
'mrproper': ["*.vcd", "*.wlf"]}
......@@ -54,6 +52,8 @@ class ToolModelsim(VsimMakefileWriter):
self.copy_rules["modelsim.ini"] = os.path.join(
"$(MODELSIM_INI_PATH)", "modelsim.ini")
self.additional_deps.append("modelsim.ini")
self._tool_info.update(ToolModelsim.TOOL_INFO)
self._clean_targets.update(ToolModelsim.CLEAN_TARGETS)
def detect_version(self, path):
"""Get version from the Mentor Modelsim program"""
......
hdlmake/tools/planahead.py
View file @ 33c3e8ea
......@@ -24,8 +24,7 @@
"""Module providing support for Xilinx PlanAhead synthesis"""
from .xilinx import ToolXilinx
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, TCLFile,
UCFFile, NGCFile, XMPFile, XCOFile)
from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile, XCOFile)
PLANAHEAD_STANDARD_LIBS = ['ieee', 'std']
......@@ -46,27 +45,17 @@ class ToolPlanAhead(ToolXilinx):
CLEAN_TARGETS = {'clean': ["planAhead_*", "planAhead.*", "run.tcl",
".Xil", "$(PROJECT).cache", "$(PROJECT).data",
" $(PROJECT).runs", "$(PROJECT).ppr"],
'mrproper': ["*.bit", "*.bin"]}
" $(PROJECT).runs", "$(PROJECT).ppr"]}
TCL_CONTROLS = {'create': 'create_project $(PROJECT) ./',
'open': 'open_project ./$(PROJECT).ppr',
'save': '',
'close': 'exit',
'synthesize': 'reset_run synth_1\n'
'launch_runs synth_1\n'
'wait_on_run synth_1',
'translate': '',
'map': '',
'par': 'reset_run impl_1\n'
'launch_runs impl_1\n'
'wait_on_run impl_1',
'bitstream': 'launch_runs impl_1 -to_step Bitgen\n'
'wait_on_run impl_1',
'install_source': '$(PROJECT).runs/impl_1/$(SYN_TOP).bit'}
TCL_CONTROLS = {'bitstream': 'launch_runs impl_1 -to_step Bitgen\n'
'wait_on_run impl_1'}
def __init__(self):
super(ToolPlanAhead, self).__init__()
self._tool_info.update(ToolPlanAhead.TOOL_INFO)
self._supported_files.extend(ToolPlanAhead.SUPPORTED_FILES)
self._clean_targets.update(ToolPlanAhead.CLEAN_TARGETS)
self._tcl_controls.update(ToolPlanAhead.TCL_CONTROLS)
def detect_version(self, path):
"""Get the Xilinx PlanAhead program version"""
......
hdlmake/tools/quartus.py
View file @ 33c3e8ea
......@@ -51,6 +51,8 @@ class ToolQuartus(ToolSyn):
SUPPORTED_FILES = [SignalTapFile, SDCFile, QIPFile, QSYSFile, DPFFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile]
HDL_FILES = [VHDLFile, VerilogFile, SVFile]
CLEAN_TARGETS = {'clean': ["*.rpt", "*.smsg", "run.tcl", "*.summary",
"*.done", "*.jdi", "*.pin", "*.qws",
"db", "incremental_db"],
......@@ -83,6 +85,11 @@ class ToolQuartus(ToolSyn):
def __init__(self):
super(ToolQuartus, self).__init__()
self._tool_info.update(ToolQuartus.TOOL_INFO)
self._hdl_files.extend(ToolQuartus.HDL_FILES)
self._supported_files.extend(ToolQuartus.SUPPORTED_FILES)
self._clean_targets.update(ToolQuartus.CLEAN_TARGETS)
self._tcl_controls.update(ToolQuartus.TCL_CONTROLS)
def detect_version(self, path):
"""Get Altera Quartus version from the binary program"""
......
hdlmake/tools/riviera.py
View file @ 33c3e8ea
......@@ -72,14 +72,14 @@ class ToolRiviera(VsimMakefileWriter):
'windows_bin': 'vsim',
'linux_bin': 'vsim'}
SUPPORTED_FILES = []
CLEAN_TARGETS = {'clean': ["*.asdb"],
'mrproper': ["*.vcd"]}
def __init__(self):
super(ToolRiviera, self).__init__()
self.vcom_flags.append("-2008")
self._tool_info.update(ToolRiviera.TOOL_INFO)
self._clean_targets.update(ToolRiviera.CLEAN_TARGETS)
def detect_version(self, path):
"""Get version from Aldec Riviera-PRO binary program"""
......
hdlmake/tools/sim_makefile_support.py
View file @ 33c3e8ea
......@@ -40,25 +40,25 @@ class VsimMakefileWriter(ToolSim):
- Riviera
"""
def __init__(self):
HDL_FILES = [VerilogFile, VHDLFile, SVFile]
def __init__(self):
super(VsimMakefileWriter, self).__init__()
# additional global flags to pass to every invocation of these commands
self.vcom_flags = ["-quiet", ]
self.vsim_flags = []
self.vlog_flags = ["-quiet", ]
self.vmap_flags = []
# These are variables that will be set in the makefile
# The key is the variable name, and the value is the variable value
self.custom_variables = {}
# Additional sim dependencies (e.g. modelsim.ini)
self.additional_deps = []
# These are files copied into your working directory by a make rule
# The key is the filename, the value is the file source path
self.copy_rules = {}
super(VsimMakefileWriter, self).__init__()
self._hdl_files.extend(VsimMakefileWriter.HDL_FILES)
def makefile_sim_options(self, top_module):
"""Print the vsim options to the Makefile"""
......@@ -124,22 +124,25 @@ class VsimMakefileWriter(ToolSim):
self.write(lib + slash_char + "." + lib + ":\n")
vmap_command = "vmap $(VMAP_FLAGS)"
self.write(' '.join(["\t(vlib", lib, "&&", vmap_command,
lib, "&&", "touch", lib + slash_char + "." + lib, ")"]))
lib, "&&", "touch", lib + slash_char +
"." + lib, ")"]))
self.write(' '.join(["||", del_command, lib, "\n"]))
self.write('\n\n')
# rules for all _primary.dat files for sv
for vlog in fileset.filter(VerilogFile):
self.write("%s: %s" % (os.path.join(vlog.library, vlog.purename,
".%s_%s" % (vlog.purename, vlog.extension())), vlog.rel_path()))
self.write("%s: %s" % (os.path.join(
vlog.library, vlog.purename,
".%s_%s" % (vlog.purename, vlog.extension())),
vlog.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile
in vlog.depends_on if dfile is not vlog]:
if dep_file in fileset:
name = dep_file.purename
extension = dep_file.extension()
self.write(" \\\n" + os.path.join(dep_file.library,
name, ".%s_%s" % (name, extension)))
self.write(" \\\n" + os.path.join(
dep_file.library, name, ".%s_%s" % (name, extension)))
else: # the file is included -> we depend directly on the file
self.write(" \\\n" + dep_file.rel_path())
self.writeln()
......@@ -154,8 +157,9 @@ class VsimMakefileWriter(ToolSim):
# self.write(incdir)
# self.writeln(vlog.vlog_opt+" $<")
compile_template = string.Template("\t\tvlog -work ${library}"
" $$(VLOG_FLAGS) ${sv_option} $${INCLUDE_DIRS} $$<")
compile_template = string.Template(
"\t\tvlog -work ${library} $$(VLOG_FLAGS) "
"${sv_option} $${INCLUDE_DIRS} $$<")
compile_line = compile_template.substitute(
library=vlog.library, sv_option="-sv"
if isinstance(vlog, SVFile) else "")
......@@ -169,8 +173,9 @@ class VsimMakefileWriter(ToolSim):
lib = vhdl.library
purename = vhdl.purename
# each .dat depends on corresponding .vhd file
self.write("%s: %s" % (os.path.join(lib, purename, "." +
purename + "_" + vhdl.extension()), vhdl.rel_path()))
self.write("%s: %s" % (os.path.join(
lib, purename, "." + purename + "_" + vhdl.extension()),
vhdl.rel_path()))
# list dependencies, do not include the target file
for dep_file in [dfile for dfile in vhdl.depends_on
if dfile is not vhdl]:
......
hdlmake/tools/vivado.py
View file @ 33c3e8ea
......@@ -23,15 +23,10 @@
"""Module providing support for Xilinx Vivado synthesis"""
import subprocess
import sys
import os
import string
import logging
from .xilinx import ToolXilinx
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, UCFFile,
NGCFile, XMPFile, XCOFile, BDFile, TCLFile)
from hdlmake.srcfile import (UCFFile, NGCFile, XMPFile,
XCOFile, BDFile, TCLFile)
VIVADO_STANDARD_LIBS = ['ieee', 'std']
......@@ -54,28 +49,18 @@ class ToolVivado(ToolXilinx):
CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log",
"$(PROJECT).cache", "$(PROJECT).data",
"$(PROJECT).runs", "$(PROJECT_FILE)"],
'mrproper': ["*.bit", "*.bin"]}
"$(PROJECT).runs", "$(PROJECT_FILE)"]}
TCL_CONTROLS = {'create': 'create_project $(PROJECT) ./',
'open': 'open_project $(PROJECT_FILE)',
'save': '',
'close': 'exit',
'synthesize': 'reset_run synth_1\n'
'launch_runs synth_1\n'
'wait_on_run synth_1',
'translate': '',
'map': '',
'par': 'reset_run impl_1\n'
'launch_runs impl_1\n'
'wait_on_run impl_1',
'bitstream':
'launch_runs impl_1 -to_step write_bitstream\n'
'wait_on_run impl_1',
'install_source': '$(PROJECT).runs/impl_1/$(SYN_TOP).bit'}
TCL_CONTROLS = {'bitstream': 'launch_runs impl_1 -to_step write_bitstream'
'\n'
'wait_on_run impl_1'}
def __init__(self):
super(ToolVivado, self).__init__()
self._tool_info.update(ToolVivado.TOOL_INFO)
self._supported_files.extend(ToolVivado.SUPPORTED_FILES)
self._clean_targets.update(ToolVivado.CLEAN_TARGETS)
self._tcl_controls.update(ToolVivado.TCL_CONTROLS)
def detect_version(self, path):
"""Get version from Xilinx Vivado binary program"""
......
hdlmake/tools/xilinx.py
View file @ 33c3e8ea
......@@ -23,15 +23,9 @@
"""Module providing generic support for Xilinx synthesis tools"""
import subprocess
import sys
import os
import string
import logging
from .make_syn import ToolSyn
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, UCFFile,
NGCFile, XMPFile, XCOFile, BDFile, TCLFile)
from hdlmake.srcfile import VHDLFile, VerilogFile, SVFile, TCLFile
VIVADO_STANDARD_LIBS = ['ieee', 'std']
......@@ -43,6 +37,8 @@ class ToolXilinx(ToolSyn):
HDL_FILES = [VHDLFile, VerilogFile, SVFile]
CLEAN_TARGETS = {'mrproper': ["*.bit", "*.bin"]}
TCL_CONTROLS = {'create': 'create_project $(PROJECT) ./',
'open': 'open_project $(PROJECT_FILE)',
'save': '',
......@@ -55,19 +51,20 @@ class ToolXilinx(ToolSyn):
'par': 'reset_run impl_1\n'
'launch_runs impl_1\n'
'wait_on_run impl_1',
'bitstream':
'launch_runs impl_1 -to_step write_bitstream\n'
'wait_on_run impl_1',
'install_source': '$(PROJECT).runs/impl_1/$(SYN_TOP).bit'}
def __init__(self):
super(ToolXilinx, self).__init__()
self._hdl_files.extend(ToolXilinx.HDL_FILES)
self._clean_targets.update(ToolXilinx.CLEAN_TARGETS)
self._tcl_controls.update(ToolXilinx.TCL_CONTROLS)
def detect_version(self, path):
"""Get version from Xilinx Vivado binary program"""
return 'unknown'
def makefile_syn_tcl(self, top_module, tcl_controls):
def makefile_syn_tcl(self, top_module):
"""Create a Xilinx synthesis project by TCL"""
tmp = "set_property {0} {1} [{2}]"
syn_device = top_module.manifest_dict["syn_device"]
......@@ -75,15 +72,15 @@ class ToolXilinx(ToolSyn):
syn_package = top_module.manifest_dict["syn_package"]
syn_top = top_module.manifest_dict["syn_top"]
create_new = []
create_new.append(tcl_controls["create"])
create_new.append(self._tcl_controls["create"])
properties = [
['part', syn_device + syn_package + syn_grade, 'current_project'],
['target_language', 'VHDL', 'current_project'],
['top', syn_top, 'get_property srcset [current_run]']]
for prop in properties:
create_new.append(tmp.format(prop[0], prop[1], prop[2]))
tcl_controls["create"] = "\n".join(create_new)
super(ToolXilinx, self).makefile_syn_tcl(top_module, tcl_controls)
self._tcl_controls["create"] = "\n".join(create_new)
super(ToolXilinx, self).makefile_syn_tcl(top_module)
def makefile_syn_files(self, fileset):
"""Write the files TCL section of the Makefile"""
......
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