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Hdlmake
Commits
5c7c8e07
Commit
5c7c8e07
authored
Mar 13, 2017
by
Javier D. Garcia-Lasheras
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Plain Diff
Handle hdl as a dictionay in Aldec Active-HDL
parent
b18e9fbc
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4 changed files
with
5 additions
and
5 deletions
+5
-5
active_hdl.py
hdlmake/tools/active_hdl.py
+3
-3
play_sim.do
tests/counter/sim/active_hdl/play_sim.do
+0
-0
Manifest.py
tests/counter/sim/active_hdl/verilog/Manifest.py
+1
-1
Manifest.py
tests/counter/sim/active_hdl/vhdl/Manifest.py
+1
-1
No files found.
hdlmake/tools/active_hdl.py
View file @
5c7c8e07
...
@@ -34,13 +34,13 @@ class ToolActiveHDL(ToolSim):
...
@@ -34,13 +34,13 @@ class ToolActiveHDL(ToolSim):
TOOL_INFO
=
{
TOOL_INFO
=
{
'name'
:
'Aldec Active-HDL'
,
'name'
:
'Aldec Active-HDL'
,
'id'
:
'a
ldec
'
,
'id'
:
'a
ctive_hdl
'
,
'windows_bin'
:
'vsimsa'
,
'windows_bin'
:
'vsimsa'
,
'linux_bin'
:
None
}
'linux_bin'
:
None
}
STANDARD_LIBS
=
[
'ieee'
,
'std'
]
STANDARD_LIBS
=
[
'ieee'
,
'std'
]
HDL_FILES
=
[
VHDLFile
,
VerilogFile
,
SVFile
]
HDL_FILES
=
{
VHDLFile
:
None
,
VerilogFile
:
None
,
SVFile
:
None
}
CLEAN_TARGETS
=
{
'clean'
:
[
"run.command"
,
"library.cfg"
,
"work"
],
CLEAN_TARGETS
=
{
'clean'
:
[
"run.command"
,
"library.cfg"
,
"work"
],
'mrproper'
:
[
"*.vcd"
,
"*.asdb"
]}
'mrproper'
:
[
"*.vcd"
,
"*.asdb"
]}
...
@@ -48,7 +48,7 @@ class ToolActiveHDL(ToolSim):
...
@@ -48,7 +48,7 @@ class ToolActiveHDL(ToolSim):
def
__init__
(
self
):
def
__init__
(
self
):
super
(
ToolActiveHDL
,
self
)
.
__init__
()
super
(
ToolActiveHDL
,
self
)
.
__init__
()
self
.
_tool_info
.
update
(
ToolActiveHDL
.
TOOL_INFO
)
self
.
_tool_info
.
update
(
ToolActiveHDL
.
TOOL_INFO
)
self
.
_hdl_files
.
extend
(
ToolActiveHDL
.
HDL_FILES
)
self
.
_hdl_files
.
update
(
ToolActiveHDL
.
HDL_FILES
)
self
.
_standard_libs
.
extend
(
ToolActiveHDL
.
STANDARD_LIBS
)
self
.
_standard_libs
.
extend
(
ToolActiveHDL
.
STANDARD_LIBS
)
self
.
_clean_targets
.
update
(
ToolActiveHDL
.
CLEAN_TARGETS
)
self
.
_clean_targets
.
update
(
ToolActiveHDL
.
CLEAN_TARGETS
)
...
...
tests/counter/sim/a
ldec
/play_sim.do
→
tests/counter/sim/a
ctive_hdl
/play_sim.do
View file @
5c7c8e07
File moved
tests/counter/sim/a
ldec
/verilog/Manifest.py
→
tests/counter/sim/a
ctive_hdl
/verilog/Manifest.py
View file @
5c7c8e07
action
=
"simulation"
action
=
"simulation"
sim_tool
=
"a
ldec
"
sim_tool
=
"a
ctive_hdl
"
sim_top
=
"counter_tb"
sim_top
=
"counter_tb"
sim_post_cmd
=
"vsimsa -do ../play_sim.do; avhdl wave.asdb"
sim_post_cmd
=
"vsimsa -do ../play_sim.do; avhdl wave.asdb"
...
...
tests/counter/sim/a
ldec
/vhdl/Manifest.py
→
tests/counter/sim/a
ctive_hdl
/vhdl/Manifest.py
View file @
5c7c8e07
action
=
"simulation"
action
=
"simulation"
sim_tool
=
"a
ldec
"
sim_tool
=
"a
ctive_hdl
"
sim_top
=
"counter_tb"
sim_top
=
"counter_tb"
sim_post_cmd
=
"vsimsa -do ../play_sim.do; avhdl wave.asdb"
sim_post_cmd
=
"vsimsa -do ../play_sim.do; avhdl wave.asdb"
...
...
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