Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Commits
61f439f5
Commit
61f439f5
authored
Aug 04, 2016
by
Javier D. Garcia-Lasheras
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Rename the Makefile printing methods
parent
3b9d64d5
Hide whitespace changes
Inline
Side-by-side
Showing
11 changed files
with
48 additions
and
48 deletions
+48
-48
makefile.py
hdlmake/action/makefile.py
+14
-14
simulation.py
hdlmake/action/simulation.py
+8
-8
synthesis.py
hdlmake/action/synthesis.py
+8
-8
active_hdl.py
hdlmake/tools/active_hdl.py
+1
-1
ghdl.py
hdlmake/tools/ghdl.py
+2
-2
isim.py
hdlmake/tools/isim.py
+3
-3
iverilog.py
hdlmake/tools/iverilog.py
+2
-2
modelsim.py
hdlmake/tools/modelsim.py
+2
-2
planahead.py
hdlmake/tools/planahead.py
+3
-3
sim_makefile_support.py
hdlmake/tools/sim_makefile_support.py
+2
-2
vivado.py
hdlmake/tools/vivado.py
+3
-3
No files found.
hdlmake/action/makefile.py
View file @
61f439f5
...
...
@@ -55,7 +55,7 @@ class ActionMakefile(Action):
if
os
.
path
.
exists
(
file_aux
):
self
.
write
(
"include
%
s
\n
"
%
file_aux
)
def
_print
_sim_top
(
self
,
top_module
):
def
makefile
_sim_top
(
self
,
top_module
):
top_parameter
=
string
.
Template
(
"""
\
TOP_MODULE := ${top_module}
PWD := $$(shell pwd)
...
...
@@ -63,7 +63,7 @@ PWD := $$(shell pwd)
self
.
writeln
(
top_parameter
.
substitute
(
top_module
=
top_module
.
manifest_dict
[
"sim_top"
]))
def
_print
_syn_top
(
self
,
top_module
,
tool_path
,
tool_info
):
def
makefile
_syn_top
(
self
,
top_module
,
tool_path
,
tool_info
):
"""Create the top part of the synthesis Makefile"""
if
path_mod
.
check_windows
():
tcl_interpreter
=
tool_info
[
"windows_bin"
]
...
...
@@ -85,7 +85,7 @@ TCL_INTERPRETER := $$(TOOL_PATH)/${tcl_interpreter}
tool_path
=
tool_path
,
top_module
=
top_module
.
manifest_dict
[
"syn_top"
]))
def
_print
_syn_tcl
(
self
,
top_module
,
tcl_controls
):
def
makefile
_syn_tcl
(
self
,
top_module
,
tcl_controls
):
"""Create the Makefile TCL dictionary for the selected tool"""
tcl_string
=
string
.
Template
(
"""
\
...
...
@@ -147,18 +147,18 @@ export TCL_BITSTREAM
tcl_bitstream
=
tcl_controls
[
"bitstream"
]))
def
_print
_sim_options
(
self
,
top_module
):
def
makefile
_sim_options
(
self
,
top_module
):
pass
def
_print
_sim_local
(
self
,
top_module
):
def
makefile
_sim_local
(
self
,
top_module
):
self
.
writeln
(
"#target for performing local simulation
\n
"
"local: sim_pre_cmd simulation sim_post_cmd
\n
"
)
def
_print
_syn_local
(
self
):
def
makefile
_syn_local
(
self
):
self
.
writeln
(
"#target for performing local synthesis
\n
"
"local: syn_pre_cmd synthesis syn_post_cmd
\n
"
)
def
_print
_syn_build
(
self
):
def
makefile
_syn_build
(
self
):
"""Generate a Makefile to handle a synthesis project"""
self
.
writeln
(
"""
\
#target for performing local synthesis
...
...
@@ -208,7 +208,7 @@ bitstream: tcl_clean tcl_open tcl_bitstream tcl_close syn_pre_bitstream_cmd run_
"""
)
def
_print
_sim_sources
(
self
,
fileset
):
def
makefile
_sim_sources
(
self
,
fileset
):
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
self
.
write
(
"VERILOG_SRC := "
)
for
vl
in
fileset
.
filter
(
VerilogFile
):
...
...
@@ -254,7 +254,7 @@ bitstream: tcl_clean tcl_open tcl_bitstream tcl_close syn_pre_bitstream_cmd run_
"
\\\n
"
)
self
.
write
(
'
\n
'
)
def
_print
_syn_command
(
self
,
top_module
):
def
makefile
_syn_command
(
self
,
top_module
):
"""Create the Makefile targets for user defined commands"""
syn_command
=
string
.
Template
(
"""
\
# User defined commands
...
...
@@ -315,7 +315,7 @@ syn_post_bitstream_cmd:
syn_post_bitstream_cmd
=
top_module
.
manifest_dict
[
"syn_post_bitstream_cmd"
]))
def
_print
_sim_command
(
self
,
top_module
):
def
makefile
_sim_command
(
self
,
top_module
):
if
top_module
.
manifest_dict
[
"sim_pre_cmd"
]:
sim_pre_cmd
=
top_module
.
manifest_dict
[
"sim_pre_cmd"
]
else
:
...
...
@@ -352,7 +352,7 @@ sim_post_cmd:
" "
+
' '
.
join
(
clean_targets
[
"mrproper"
])
self
.
writeln
(
tmp
)
def
_print
_syn_clean
(
self
,
clean_targets
):
def
makefile
_syn_clean
(
self
,
clean_targets
):
"""Print the Makefile clean target for synthesis"""
self
.
_print_tool_clean
(
clean_targets
)
self
.
writeln
(
"
\t\t
"
+
path_mod
.
del_command
()
+
...
...
@@ -361,17 +361,17 @@ sim_post_cmd:
" tcl_synthesize tcl_translate tcl_map tcl_par tcl_bitstream"
)
self
.
_print_tool_mrproper
(
clean_targets
)
def
_print
_sim_clean
(
self
,
clean_targets
):
def
makefile
_sim_clean
(
self
,
clean_targets
):
"""Print the Makefile clean target for synthesis"""
self
.
_print_tool_clean
(
clean_targets
)
self
.
_print_tool_mrproper
(
clean_targets
)
def
_print
_sim_phony
(
self
,
top_module
):
def
makefile
_sim_phony
(
self
,
top_module
):
"""Print simulation PHONY target list to the Makefile"""
self
.
writeln
(
".PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation"
)
def
_print
_syn_phony
(
self
):
def
makefile
_syn_phony
(
self
):
"""Print synthesis PHONY target list to the Makefile"""
self
.
writeln
(
".PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis"
)
...
...
hdlmake/action/simulation.py
View file @
61f439f5
...
...
@@ -97,11 +97,11 @@ class ActionSimulation(
# dep_solver.solve(dep_files)
# tool_object.generate_simulation_makefile(dep_files, top_module)
tool_object
.
_print
_sim_top
(
top_module
)
tool_object
.
_print
_sim_options
(
top_module
)
tool_object
.
_print
_sim_local
(
top_module
)
tool_object
.
_print
_sim_sources
(
dep_files
)
tool_object
.
_print
_sim_compilation
(
dep_files
,
top_module
)
tool_object
.
_print
_sim_command
(
top_module
)
tool_object
.
_print
_sim_clean
(
tool_object
.
CLEAN_TARGETS
)
tool_object
.
_print
_sim_phony
(
top_module
)
tool_object
.
makefile
_sim_top
(
top_module
)
tool_object
.
makefile
_sim_options
(
top_module
)
tool_object
.
makefile
_sim_local
(
top_module
)
tool_object
.
makefile
_sim_sources
(
dep_files
)
tool_object
.
makefile
_sim_compilation
(
dep_files
,
top_module
)
tool_object
.
makefile
_sim_command
(
top_module
)
tool_object
.
makefile
_sim_clean
(
tool_object
.
CLEAN_TARGETS
)
tool_object
.
makefile
_sim_phony
(
top_module
)
hdlmake/action/synthesis.py
View file @
61f439f5
...
...
@@ -226,12 +226,12 @@ end sdb_meta_pkg;""")
module
=
self
.
get_module_by_path
(
"."
))])
tool_object
.
_print_incl_makefiles
(
top_module
)
tool_object
.
_print
_syn_top
(
top_module
,
tool_path
,
tool_info
)
tool_object
.
_print
_syn_tcl
(
top_module
,
tool_ctrl
)
tool_object
.
_print
_syn_files
(
fileset
)
tool_object
.
_print
_syn_local
()
tool_object
.
_print
_syn_command
(
top_module
)
tool_object
.
_print
_syn_build
()
tool_object
.
_print
_syn_clean
(
tool_object
.
CLEAN_TARGETS
)
tool_object
.
_print
_syn_phony
()
tool_object
.
makefile
_syn_top
(
top_module
,
tool_path
,
tool_info
)
tool_object
.
makefile
_syn_tcl
(
top_module
,
tool_ctrl
)
tool_object
.
makefile
_syn_files
(
fileset
)
tool_object
.
makefile
_syn_local
()
tool_object
.
makefile
_syn_command
(
top_module
)
tool_object
.
makefile
_syn_build
()
tool_object
.
makefile
_syn_clean
(
tool_object
.
CLEAN_TARGETS
)
tool_object
.
makefile
_syn_phony
()
logging
.
info
(
name
+
" project file generated."
)
hdlmake/tools/active_hdl.py
View file @
61f439f5
...
...
@@ -49,7 +49,7 @@ class ToolActiveHDL(ActionMakefile):
"""Get the version from the Aldec-HDL binary program"""
pass
def
_print
_sim_compilation
(
self
,
fileset
,
top_module
):
def
makefile
_sim_compilation
(
self
,
fileset
,
top_module
):
"""Print Makefile compilation target for Aldec Active-HDL simulator"""
self
.
writeln
(
"simulation:"
)
self
.
writeln
(
"
\t\t
echo
\"
# Active-HDL command file,"
...
...
hdlmake/tools/ghdl.py
View file @
61f439f5
...
...
@@ -52,7 +52,7 @@ class ToolGHDL(ActionMakefile):
"""Get tool version for GHDL"""
pass
def
_print
_sim_options
(
self
,
top_module
):
def
makefile
_sim_options
(
self
,
top_module
):
"""Print the GHDL options to the Makefile"""
if
top_module
.
manifest_dict
[
"ghdl_opt"
]:
ghdl_opt
=
top_module
.
manifest_dict
[
"ghdl_opt"
]
...
...
@@ -63,7 +63,7 @@ class ToolGHDL(ActionMakefile):
self
.
writeln
(
ghdl_string
.
substitute
(
ghdl_opt
=
ghdl_opt
))
def
_print
_sim_compilation
(
self
,
fileset
,
top_module
):
def
makefile
_sim_compilation
(
self
,
fileset
,
top_module
):
"""Print the GDHL simulation compilation target"""
self
.
writeln
(
"simulation:"
)
self
.
writeln
(
"
\t\t
# Analyze sources"
)
...
...
hdlmake/tools/isim.py
View file @
61f439f5
...
...
@@ -80,7 +80,7 @@ class ToolISim(ActionMakefile):
return
None
return
isim_version
def
_print
_sim_top
(
self
,
top_module
):
def
makefile
_sim_top
(
self
,
top_module
):
"""Print the top section of the Makefile for Xilinx ISim"""
self
.
writeln
(
"""## variables #############################
PWD := $(shell pwd)
...
...
@@ -91,7 +91,7 @@ XILINX_INI_PATH := """ + self.__get_xilinxsim_ini_dir(top_module.pool.env) +
"""
"""
)
def
_print
_sim_options
(
self
,
top_module
):
def
makefile
_sim_options
(
self
,
top_module
):
"""Print the Xilinx ISim simulation options in the Makefile"""
self
.
writeln
(
"""VHPCOMP_FLAGS := -intstyle default
\
-incremental -initfile xilinxsim.ini
...
...
@@ -101,7 +101,7 @@ VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ +
top_module
.
manifest_dict
[
"vlog_opt"
])
+
"""
"""
)
def
_print
_sim_compilation
(
self
,
fileset
,
top_module
):
def
makefile
_sim_compilation
(
self
,
fileset
,
top_module
):
"""Print the compile simulation target for Xilinx ISim"""
make_preambule_p2
=
"""## rules #################################
simulation: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ) fuse
...
...
hdlmake/tools/iverilog.py
View file @
61f439f5
...
...
@@ -67,7 +67,7 @@ class ToolIVerilog(ActionMakefile):
version
=
iverilog
.
stdout
.
readlines
()[
0
]
.
strip
()
return
version
def
_print
_sim_compilation
(
self
,
fileset
,
top_module
):
def
makefile
_sim_compilation
(
self
,
fileset
,
top_module
):
"""Generate compile simulation Makefile target for IVerilog"""
self
.
writeln
(
"simulation:"
)
...
...
@@ -94,7 +94,7 @@ class ToolIVerilog(ActionMakefile):
self
.
writeln
(
"
\t\t
iverilog $(IVERILOG_OPT) -s $(TOP_MODULE)"
" -o $(TOP_MODULE).vvp -c run.command"
)
def
_print
_sim_options
(
self
,
top_module
):
def
makefile
_sim_options
(
self
,
top_module
):
"""Print the IVerilog options to the Makefile"""
if
top_module
.
manifest_dict
[
"iverilog_opt"
]:
iverilog_opt
=
top_module
.
manifest_dict
[
"iverilog_opt"
]
...
...
hdlmake/tools/modelsim.py
View file @
61f439f5
...
...
@@ -59,7 +59,7 @@ class ToolModelsim(VsimMakefileWriter):
"""Get version from the Mentor Modelsim program"""
pass
def
_print
_sim_options
(
self
,
top_module
):
def
makefile
_sim_options
(
self
,
top_module
):
"""Print the Modelsim options to the Makefile"""
if
top_module
.
pool
.
env
[
"modelsim_path"
]:
modelsim_ini_path
=
os
.
path
.
join
(
...
...
@@ -68,4 +68,4 @@ class ToolModelsim(VsimMakefileWriter):
else
:
modelsim_ini_path
=
os
.
path
.
join
(
"$(HDLMAKE_MODELSIM_PATH)"
,
".."
)
self
.
custom_variables
[
"MODELSIM_INI_PATH"
]
=
modelsim_ini_path
super
(
ToolModelsim
,
self
)
.
_print
_sim_options
(
top_module
)
super
(
ToolModelsim
,
self
)
.
makefile
_sim_options
(
top_module
)
hdlmake/tools/planahead.py
View file @
61f439f5
...
...
@@ -72,7 +72,7 @@ class ToolPlanAhead(ActionMakefile):
"""Get the Xilinx PlanAhead program version"""
return
'unknown'
def
_print
_syn_tcl
(
self
,
top_module
,
tcl_controls
):
def
makefile
_syn_tcl
(
self
,
top_module
,
tcl_controls
):
"""Create a Xilinx PlanAhead project"""
tmp
=
"set_property {0} {1} [{2}]"
syn_device
=
top_module
.
manifest_dict
[
"syn_device"
]
...
...
@@ -88,9 +88,9 @@ class ToolPlanAhead(ActionMakefile):
for
prop
in
properties
:
create_new
.
append
(
tmp
.
format
(
prop
[
0
],
prop
[
1
],
prop
[
2
]))
tcl_controls
[
"create"
]
=
"
\n
"
.
join
(
create_new
)
super
(
ToolPlanAhead
,
self
)
.
_print
_syn_tcl
(
top_module
,
tcl_controls
)
super
(
ToolPlanAhead
,
self
)
.
makefile
_syn_tcl
(
top_module
,
tcl_controls
)
def
_print
_syn_files
(
self
,
fileset
):
def
makefile
_syn_files
(
self
,
fileset
):
"""Create a Xilinx PlanAhead project"""
self
.
writeln
(
"define TCL_FILES"
)
tmp
=
"add_files -norecurse {0}"
...
...
hdlmake/tools/sim_makefile_support.py
View file @
61f439f5
...
...
@@ -60,7 +60,7 @@ class VsimMakefileWriter(ActionMakefile):
self
.
copy_rules
=
{}
super
(
VsimMakefileWriter
,
self
)
.
__init__
()
def
_print
_sim_options
(
self
,
top_module
):
def
makefile
_sim_options
(
self
,
top_module
):
"""Print the vsim options to the Makefile"""
self
.
vlog_flags
.
append
(
self
.
__get_rid_of_vsim_incdirs
(
...
...
@@ -78,7 +78,7 @@ class VsimMakefileWriter(ActionMakefile):
self
.
writeln
(
"VLOG_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vlog_flags
)))
self
.
writeln
(
"VMAP_FLAGS :=
%
s"
%
(
' '
.
join
(
self
.
vmap_flags
)))
def
_print
_sim_compilation
(
self
,
fileset
,
top_module
):
def
makefile
_sim_compilation
(
self
,
fileset
,
top_module
):
"""Write a properly formatted Makefile for the simulator.
The Makefile format is shared, but flags, dependencies, clean rules,
etc are defined by the specific tool.
...
...
hdlmake/tools/vivado.py
View file @
61f439f5
...
...
@@ -81,7 +81,7 @@ class ToolVivado(ActionMakefile):
"""Get version from Xilinx Vivado binary program"""
return
'unknown'
def
_print
_syn_tcl
(
self
,
top_module
,
tcl_controls
):
def
makefile
_syn_tcl
(
self
,
top_module
,
tcl_controls
):
"""Create a Xilinx Vivado project"""
tmp
=
"set_property {0} {1} [{2}]"
syn_device
=
top_module
.
manifest_dict
[
"syn_device"
]
...
...
@@ -97,9 +97,9 @@ class ToolVivado(ActionMakefile):
for
prop
in
properties
:
create_new
.
append
(
tmp
.
format
(
prop
[
0
],
prop
[
1
],
prop
[
2
]))
tcl_controls
[
"create"
]
=
"
\n
"
.
join
(
create_new
)
super
(
ToolVivado
,
self
)
.
_print
_syn_tcl
(
top_module
,
tcl_controls
)
super
(
ToolVivado
,
self
)
.
makefile
_syn_tcl
(
top_module
,
tcl_controls
)
def
_print
_syn_files
(
self
,
fileset
):
def
makefile
_syn_files
(
self
,
fileset
):
"""Create a Xilinx Vivado project"""
self
.
writeln
(
"define TCL_FILES"
)
tmp
=
"add_files -norecurse {0}"
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment