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Hdlmake
Commit 6d763a1d authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Fix minor style issues

parent 918438b5
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Showing with 19 additions and 14 deletions
hdlmake/fetch/git.py
View file @ 6d763a1d
...@@ -49,9 +49,9 @@ class Git(Fetcher): ...@@ -49,9 +49,9 @@ class Git(Fetcher):
shell=True) shell=True)
tree_root_line = tree_root_cmd.stdout.readlines()[0].strip() tree_root_line = tree_root_cmd.stdout.readlines()[0].strip()
return tree_root_line return tree_root_line
except CalledProcessError as e: except CalledProcessError as process_error:
print e.output logging.error("Cannot get the top level!: %s",
logging.error("Cannot get the top level!") process_error.output)
quit() quit()
@staticmethod @staticmethod
...@@ -74,9 +74,9 @@ class Git(Fetcher): ...@@ -74,9 +74,9 @@ class Git(Fetcher):
return None return None
else: else:
return None return None
except CalledProcessError as e: except CalledProcessError as process_error:
print e.output logging.error("Cannot get the submodule status!: %s",
logging.error("Cannot get the submodule status!") process_error.output)
quit() quit()
def fetch(self, module): def fetch(self, module):
...@@ -99,7 +99,7 @@ class Git(Fetcher): ...@@ -99,7 +99,7 @@ class Git(Fetcher):
else: else:
logging.info("Updating git module %s", mod_path) logging.info("Updating git module %s", mod_path)
checkout_id = None checkout_id = None
if module.branch is not None: if module.branch is not None:
checkout_id = module.branch checkout_id = module.branch
logging.debug("Git branch requested: %s", checkout_id) logging.debug("Git branch requested: %s", checkout_id)
elif module.revision is not None: elif module.revision is not None:
......
hdlmake/module/content.py
View file @ 6d763a1d
...@@ -110,8 +110,10 @@ class ModuleContent(ModuleCore): ...@@ -110,8 +110,10 @@ class ModuleContent(ModuleCore):
# Included Makefiles # Included Makefiles
included_makefiles_aux = [] included_makefiles_aux = []
if "incl_makefiles" in self.manifest_dict: if "incl_makefiles" in self.manifest_dict:
if isinstance(self.manifest_dict["incl_makefiles"], six.string_types): if isinstance(self.manifest_dict["incl_makefiles"],
included_makefiles_aux.append(self.manifest_dict["incl_makefiles"]) six.string_types):
included_makefiles_aux.append(
self.manifest_dict["incl_makefiles"])
else: # list else: # list
included_makefiles_aux = self.manifest_dict["incl_makefiles"][:] included_makefiles_aux = self.manifest_dict["incl_makefiles"][:]
makefiles_paths = self._make_list_of_paths(included_makefiles_aux) makefiles_paths = self._make_list_of_paths(included_makefiles_aux)
......
hdlmake/tools/diamond.py
View file @ 6d763a1d
...@@ -46,7 +46,7 @@ class ToolDiamond(ToolSyn): ...@@ -46,7 +46,7 @@ class ToolDiamond(ToolSyn):
SUPPORTED_FILES = { SUPPORTED_FILES = {
EDFFile: _LATTICE_SOURCE.format('add'), EDFFile: _LATTICE_SOURCE.format('add'),
LPFFile: _LATTICE_SOURCE.format('add -exclude') + '\n ' + LPFFile: _LATTICE_SOURCE.format('add -exclude') + '\n ' +
_LATTICE_SOURCE.format('enable')} _LATTICE_SOURCE.format('enable')}
HDL_FILES = { HDL_FILES = {
......
hdlmake/tools/quartus.py
View file @ 6d763a1d
...@@ -53,7 +53,7 @@ class ToolQuartus(ToolSyn): ...@@ -53,7 +53,7 @@ class ToolQuartus(ToolSyn):
SUPPORTED_FILES = { SUPPORTED_FILES = {
SignalTapFile: _QUARTUS_SOURCE.format('SIGNALTAP_FILE'), SignalTapFile: _QUARTUS_SOURCE.format('SIGNALTAP_FILE'),
SDCFile: _QUARTUS_SOURCE.format('SDC_FILE'), SDCFile: _QUARTUS_SOURCE.format('SDC_FILE'),
QIPFile: _QUARTUS_SOURCE.format('QIP_FILE'), QIPFile: _QUARTUS_SOURCE.format('QIP_FILE'),
QSYSFile: _QUARTUS_SOURCE.format('QSYS_FILE'), QSYSFile: _QUARTUS_SOURCE.format('QSYS_FILE'),
DPFFile: _QUARTUS_SOURCE.format('MISC_FILE'), DPFFile: _QUARTUS_SOURCE.format('MISC_FILE'),
QSFFile: _QUARTUS_SOURCE.format('SOURCE_TCL_SCRIPT_FILE'), QSFFile: _QUARTUS_SOURCE.format('SOURCE_TCL_SCRIPT_FILE'),
...@@ -66,9 +66,12 @@ class ToolQuartus(ToolSyn): ...@@ -66,9 +66,12 @@ class ToolQuartus(ToolSyn):
_QUARTUS_LIBRARY = " -library {0}".format('work') _QUARTUS_LIBRARY = " -library {0}".format('work')
HDL_FILES = { HDL_FILES = {
VHDLFile: _QUARTUS_SOURCE.format('VHDL_FILE') + _QUARTUS_LIBRARY, VHDLFile: _QUARTUS_SOURCE.format('VHDL_FILE') +
VerilogFile: _QUARTUS_SOURCE.format('SYSTEMVERILOG_FILE') + _QUARTUS_LIBRARY, _QUARTUS_LIBRARY,
SVFile: _QUARTUS_SOURCE.format('VERILOG_FILE') + _QUARTUS_LIBRARY} VerilogFile: _QUARTUS_SOURCE.format('SYSTEMVERILOG_FILE') +
_QUARTUS_LIBRARY,
SVFile: _QUARTUS_SOURCE.format('VERILOG_FILE') +
_QUARTUS_LIBRARY}
CLEAN_TARGETS = {'clean': ["*.rpt", "*.smsg", "run.tcl", "*.summary", CLEAN_TARGETS = {'clean': ["*.rpt", "*.smsg", "run.tcl", "*.summary",
"*.done", "*.jdi", "*.pin", "*.qws", "*.done", "*.jdi", "*.pin", "*.qws",
......
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