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Hdlmake
Commit 712da06f authored by Tristan Gingold's avatar Tristan Gingold
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Add xvhdl options for vivado 

By thunderthumbs
parent 9fa7d06c
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Showing with 34 additions and 3 deletions
docs/index.rst
View file @ 712da06f
......@@ -1547,6 +1547,15 @@ NVC specific variables:
| nvc_elab_opt | str | Additional elaboration options for nvc | "" |
+------------------+--------------+-----------------------------------------------------------------+-----------+
Vivado Sim specific variables:
+----------------+--------------+-----------------------------------------------------------------+-----------+
| Name | Type | Description | Default |
+================+==============+=================================================================+===========+
| xvhdl_opt | str | Additional options for vhdl compilation | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
| xvlog_opt | str | Additional options for verilog compilation | "" |
+----------------+--------------+-----------------------------------------------------------------+-----------+
Synthesis variables
-------------------
......
hdlmake/manifest_parser/manifestparser.py
View file @ 712da06f
......@@ -267,6 +267,17 @@ class ManifestParser(ConfigParser):
help="Additional options for GHDL",
type='')
self.add_delimiter()
vivado_sim_options = [
{'name': 'xvlog_opt',
'default': "",
'help': "Additional options for verilog",
'type': ''},
{'name': 'xvhdl_opt',
'default': "",
'help': "Additional options for vhdl",
'type': ''}]
self.add_option_list(vivado_sim_options)
self.add_delimiter()
def add_option_list(self, option_list):
"""Add to the parser a list with the options and their keys"""
......
hdlmake/tools/vivado_sim.py
View file @ 712da06f
......@@ -49,8 +49,8 @@ class ToolVivadoSim(ToolXilinxProject, MakefileSim):
"work", "xsim.dir"],
'mrproper': ["*.wdb", "*.vcd"]}
SIMULATOR_CONTROLS = {'vlog': 'xvlog $<',
'vhdl': 'xvhdl --work {work} $<',
SIMULATOR_CONTROLS = {'vlog': 'xvlog $(XVLOG_OPT) $<',
'vhdl': 'xvhdl --work {work} $(XVHDL_OPT) $<',
'compiler': 'xelab -debug all $(TOP_MODULE) '
'-s $(TOP_MODULE)'}
......@@ -69,6 +69,13 @@ class ToolVivadoSim(ToolXilinxProject, MakefileSim):
self.writeln("\t{} $<".format(self.get_tool_bin()))
self.writeln()
def _makefile_sim_options(self):
"""Print the Vivado Sim options to the Makefile"""
xvhdl_opt = self.manifest_dict.get("xvhdl_opt", '')
self.writeln("XVHDL_OPT := {xvhdl_opt}\n".format(xvhdl_opt=xvhdl_opt))
xvlog_opt = self.manifest_dict.get("xvlog_opt", '')
self.writeln("XVLOG_OPT := {xvlog_opt}\n".format(xvlog_opt=xvlog_opt))
def _makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for Vivado Simulator"""
libs = self.get_all_libs()
......
testsuite/019vsim/Makefile.ref
View file @ 712da06f
......@@ -5,6 +5,10 @@
TOP_MODULE := gate
XVHDL_OPT :=
XVLOG_OPT :=
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
......@@ -21,7 +25,7 @@ simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
xelab -debug all $(TOP_MODULE) -s $(TOP_MODULE)
work/gate/.gate_vhdl: ../files/gate.vhdl
xvhdl --work work $<
xvhdl --work work $(XVHDL_OPT) $<
@mkdir -p $(dir $@) && touch $@
......
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