Merge branch 'nvc-support' into 'develop'

NVC: Add new variables for setting analysis and elaboration flags, update documentation See merge request !28

Merge branch 'nvc-support' into 'develop'
NVC: Add new variables for setting analysis and elaboration flags, update documentation See merge request !28
9fa7d06c · Tristan Gingold · 24aa6947 · 30766011 · 9fa7d06c · 9fa7d06c
Commit 9fa7d06c authored Jan 25, 2024 by Tristan Gingold
5 changed files
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -131,6 +131,8 @@ Supported Tools
 +--------------------------+-----------+------------+
 | GHDL                     | n.a.      | VHDL       |
 +--------------------------+-----------+------------+
+| NVC                      | n.a.      | VHDL       |
+--------------------------+-----------+------------+

 Supported Operating Systems
 ---------------------------
@@ -1533,6 +1535,17 @@ GHDL specific variables:
 | ghdl_opt       | str          | Additional options for ghdl                                     | ""        |
 +----------------+--------------+-----------------------------------------------------------------+-----------+

+NVC specific variables:
+
+------------------+--------------+-----------------------------------------------------------------+-----------+
+| Name             | Type         | Description                                                     | Default   |
+==================+==============+=================================================================+===========+
+| nvc_opt          | str          | Additional global options for nvc                               | ""        |
+------------------+--------------+-----------------------------------------------------------------+-----------+
+| nvc_analysis_opt | str          | Additional analysis options for nvc                             | ""        |
+------------------+--------------+-----------------------------------------------------------------+-----------+
+| nvc_elab_opt     | str          | Additional elaboration options for nvc                          | ""        |
+------------------+--------------+-----------------------------------------------------------------+-----------+


 Synthesis variables

--- a/hdlmake/tools/nvc.py
+++ b/hdlmake/tools/nvc.py
@@ -48,8 +48,8 @@ class ToolNVC(MakefileSim):
                     'mrproper': ["*.vcd"]}

    SIMULATOR_CONTROLS = {'vlog': None,
-                          'vhdl': '$(NVC) --work={work} $(NVC_OPT) -a  $<',
-                          'compiler': '$(NVC) $(NVC_OPT) -e $(TOP_MODULE)'}
+                          'vhdl': '$(NVC) --work={work} $(NVC_OPT) -a $(NVC_ANALYSIS_OPT)  $<',
+                          'compiler': '$(NVC) $(NVC_OPT) -e $(NVC_ELAB_OPT) $(TOP_MODULE)'}

    def __init__(self):
        super(ToolNVC, self).__init__()
@@ -58,7 +58,11 @@ class ToolNVC(MakefileSim):
        """Print the NVC options to the Makefile"""
        self.writeln("NVC := nvc")
        nvc_opt = self.manifest_dict.get("nvc_opt", '')
+        nvc_analysis_opt = self.manifest_dict.get("nvc_analysis_opt", '')
+        nvc_elab_opt = self.manifest_dict.get("nvc_elab_opt", '')
        self.writeln("NVC_OPT := {nvc_opt}\n".format(nvc_opt=nvc_opt))
+        self.writeln("NVC_ANALYSIS_OPT := {nvc_analysis_opt}\n".format(nvc_analysis_opt=nvc_analysis_opt))
+        self.writeln("NVC_ELAB_OPT := {nvc_elab_opt}\n".format(nvc_elab_opt=nvc_elab_opt))

    def _makefile_sim_compilation(self):
        """Print the NVC simulation compilation target"""

--- a/tests/counter/sim/nvc/vhdl/Manifest.py
+++ b/tests/counter/sim/nvc/vhdl/Manifest.py
+action = "simulation"
+sim_tool = "nvc"
+sim_top = "counter_tb"
+
+sim_post_cmd = "nvc -r counter_tb --stop-time=6us --format=vcd --wave=counter_tb.vcd"
+
+modules = {
+  "local" : [ "../../../testbench/counter_tb/vhdl" ],
+}
--- a/testsuite/128nvc/Makefile.ref
+++ b/testsuite/128nvc/Makefile.ref
@@ -8,6 +8,10 @@ TOP_MODULE := gate3
 NVC := nvc
 NVC_OPT := --std=2008

+NVC_ANALYSIS_OPT := --psl
+
+NVC_ELAB_OPT := --verbose
+
 #target for performing local simulation
 local: sim_pre_cmd simulation sim_post_cmd

@@ -23,17 +27,17 @@ LIBS := work
 LIB_IND := work/.work

 simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
-		$(NVC) $(NVC_OPT) -e $(TOP_MODULE)
+		$(NVC) $(NVC_OPT) -e $(NVC_ELAB_OPT) $(TOP_MODULE)


 work/gate/.gate_vhdl: ../files/gate.vhdl
-		$(NVC) --work=work $(NVC_OPT) -a  $<
+		$(NVC) --work=work $(NVC_OPT) -a $(NVC_ANALYSIS_OPT)  $<
 		@mkdir -p $(dir $@) && touch $@


 work/gate3/.gate3_vhd: ../files/gate3.vhd \
 work/gate/.gate_vhdl
-		$(NVC) --work=work $(NVC_OPT) -a  $<
+		$(NVC) --work=work $(NVC_OPT) -a $(NVC_ANALYSIS_OPT)  $<
 		@mkdir -p $(dir $@) && touch $@



--- a/testsuite/128nvc/Manifest.py
+++ b/testsuite/128nvc/Manifest.py
@@ -2,6 +2,8 @@ action = "simulation"

 sim_tool="nvc"
 nvc_opt="--std=2008"
+nvc_analysis_opt="--psl"
+nvc_elab_opt="--verbose"

 top_module = "gate3"