Commit 83516aa1 authored by Benny Simonsen's avatar Benny Simonsen

testsuite/files/gate.vhdl: Port map: reorder to i,o

All places gate is used the order is i, o.
The change does not affect pytest testall, but needed to compile the testsuite tests.
parent f41e6a57
entity gate is
port (o : out bit;
i : in bit);
port (i : in bit;
o : out bit);
end gate;
architecture behav of gate is
......
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