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Hdlmake
Commits
969a2617
Commit
969a2617
authored
Jul 31, 2016
by
Javier D. Garcia-Lasheras
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Refactoring and renaming merge and tree actions
parent
3fd3c0a9
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4 changed files
with
24 additions
and
36 deletions
+24
-36
__init__.py
hdlmake/action/__init__.py
+2
-2
merge.py
hdlmake/action/merge.py
+19
-31
tree.py
hdlmake/action/tree.py
+1
-1
module_pool.py
hdlmake/module_pool.py
+2
-2
No files found.
hdlmake/action/__init__.py
View file @
969a2617
...
...
@@ -23,8 +23,8 @@
from
.check_condition
import
CheckCondition
from
.check_manifest
import
CheckManifest
from
.core
import
ActionCore
from
.merge
_cores
import
MergeCores
from
.tree
import
Tree
from
.merge
import
ActionMerge
from
.tree
import
Action
Tree
from
.synthesis
import
ActionSynthesis
from
.simulation
import
GenerateSimulationMakefile
...
...
hdlmake/action/merge
_cores
.py
→
hdlmake/action/merge.py
View file @
969a2617
...
...
@@ -32,33 +32,30 @@ from hdlmake.vlog_parser import VerilogPreprocessor
from
.action
import
Action
class
MergeCores
(
Action
):
def
_check_merge_cores
(
self
):
self
.
_check_manifest_variable_is_equal_to
(
"action"
,
"synthesis"
)
if
not
self
.
env
.
options
.
dest
:
logging
.
error
(
"--dest must be given for merge-cores"
)
sys
.
exit
(
"Exiting"
)
class
ActionMerge
(
Action
):
def
merge_cores
(
self
):
self
.
_check_all_fetched_or_quit
()
self
.
_check_merge_cores
()
logging
.
info
(
"Merging all cores into one source file per language."
)
flist
=
self
.
build_file_set
()
base
=
self
.
env
.
options
.
dest
f_out
=
open
(
base
+
".vhd"
,
"w"
)
f_out
.
write
(
"
\n\n\n\n
"
)
f_out
.
write
(
"------------------------------ WARNING -------------------------------
\n
"
)
f_out
.
write
(
"-- This code has been generated by hdlmake --merge-cores option --
\n
"
)
f_out
.
write
(
"-- It is provided for your convenience, to spare you from adding --
\n
"
)
f_out
.
write
(
"-- lots of individual source files to ISE/Modelsim/Quartus projects --
\n
"
)
f_out
.
write
(
"-- mainly for Windows users. Please DO NOT MODIFY this file. If you --
\n
"
)
f_out
.
write
(
"-- need to change something inside, edit the original source file --
\n
"
)
f_out
.
write
(
"-- and re-genrate the merged version! --
\n
"
)
f_out
.
write
(
"----------------------------------------------------------------------
\n
"
)
f_out
.
write
(
"
\n\n\n\n
"
)
file_header
=
(
"
\n\n\n\n
"
"------------------------------ WARNING -------------------------------
\n
"
"-- This code has been generated by hdlmake --merge-cores option --
\n
"
"-- It is provided for your convenience, to spare you from adding --
\n
"
"-- lots of individual source files to ISE/Modelsim/Quartus projects --
\n
"
"-- mainly for Windows users. Please DO NOT MODIFY this file. If you --
\n
"
"-- need to change something inside, edit the original source file --
\n
"
"-- and re-genrate the merged version! --
\n
"
"----------------------------------------------------------------------
\n
"
"
\n\n\n\n
"
)
# Generate a VHDL file containing all the required VHDL files
f_out
=
open
(
base
+
".vhd"
,
"w"
)
f_out
.
write
(
file_header
)
for
vhdl
in
flist
.
filter
(
VHDLFile
):
f_out
.
write
(
"
\n\n
--- File:
%
s ----
\n
"
%
vhdl
.
rel_path
())
f_out
.
write
(
"--- Source:
%
s
\n
"
%
vhdl
.
module
.
url
)
...
...
@@ -69,19 +66,9 @@ class MergeCores(Action):
#print("VHDL: %s" % vhdl.rel_path())
f_out
.
close
()
# Generate a VHDL file containing all the required VHDL files
f_out
=
open
(
base
+
".v"
,
"w"
)
f_out
.
write
(
"
\n\n\n\n
"
)
f_out
.
write
(
"////////////////////////////// WARNING ///////////////////////////////
\n
"
)
f_out
.
write
(
"// This code has been generated by hdlmake --merge-cores option //
\n
"
)
f_out
.
write
(
"// It is provided for your convenience, to spare you from adding //
\n
"
)
f_out
.
write
(
"// lots of individual source files to ISE/Modelsim/Quartus projects //
\n
"
)
f_out
.
write
(
"// mainly for Windows users. Please DO NOT MODIFY this file. If you //
\n
"
)
f_out
.
write
(
"// need to change something inside, edit the original source file //
\n
"
)
f_out
.
write
(
"// and re-genrate the merged version! //
\n
"
)
f_out
.
write
(
"//////////////////////////////////////////////////////////////////////
\n
"
)
f_out
.
write
(
"
\n\n\n\n
"
)
f_out
.
write
(
file_header
)
for
vlog
in
flist
.
filter
(
VerilogFile
):
f_out
.
write
(
"
\n\n
// File:
%
s
\n
"
%
vlog
.
rel_path
())
f_out
.
write
(
"// Source:
%
s
\n
"
%
vlog
.
module
.
url
)
...
...
@@ -95,6 +82,7 @@ class MergeCores(Action):
f_out
.
write
(
vpp
.
preprocess
(
vlog
.
rel_path
()))
f_out
.
close
()
# Handling NGC files
current_path
=
os
.
getcwd
()
for
ngc
in
flist
.
filter
(
NGCFile
):
import
shutil
...
...
hdlmake/action/tree.py
View file @
969a2617
...
...
@@ -24,7 +24,7 @@ from hdlmake.util import path
import
logging
class
Tree
(
Action
):
class
Action
Tree
(
Action
):
def
generate_tree
(
self
):
try
:
import
networkx
as
nx
...
...
hdlmake/module_pool.py
View file @
969a2617
...
...
@@ -35,13 +35,13 @@ from .util import path as path_mod
from
.
import
fetch
from
.env
import
Env
from
.action
import
(
CheckManifest
,
CheckCondition
,
ActionCore
,
MergeCores
,
Tree
,
GenerateSimulationMakefile
,
ActionMerge
,
Action
Tree
,
GenerateSimulationMakefile
,
ActionSynthesis
,
QsysHwTclUpdate
)
class
ModulePool
(
list
,
CheckManifest
,
CheckCondition
,
ActionCore
,
MergeCores
,
Tree
,
GenerateSimulationMakefile
,
ActionMerge
,
Action
Tree
,
GenerateSimulationMakefile
,
ActionSynthesis
,
QsysHwTclUpdate
):
"""
...
...
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